參數(shù)資料
型號： 73S1209F-EB
廠商： Maxim Integrated Products
文件頁數(shù)： 63/123頁
文件大?。?/td> 0K
描述： BOARD EVAL 73S1209F DOC/CD CABLE
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： *
嵌入式： *
已用 IC / 零件： *
主要屬性： *
次要屬性： *
已供物品： 板，線纜，CD，電源
73S1209F Data Sheet
DS_1209F_004
1.7.5 Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be
configured for counter or timer operations.
In timer mode, the register is incremented every machine cycle, meaning that it counts up after every 12
periods of the MPU clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding input
signal T0 or T1 (T0 and T1 are the timer gating inputs derived from USR[0:7] pins, see the User (USR)
Ports section). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count
rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure
proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD
and TCON) are used to select the appropriate mode.
The Timer 0 load registers are designated as TL0 and TH0 and the Timer 1 load registers are designated
as TL1 and TH1.
Timer/Counter Mode Control Register (TMOD): 0x89
0x00
Table 40: The TMOD Register
MSB
LSB
GATE
C/T
M1
M0
GATE
C/T
M1
M0
Timer 1
Timer 0
Bits TR1 and TR0 in the TCON register start their associated timers when set.
Table 41: TMOD Register Bit Description
Bit
Symbol
Function
TMOD.7
TMOD.3
Gate
If set, enables external gate control (USR pin(s) connected to T0 or T1
for Counter 0 or 1, respectively). When T0 or T1 is high, and TRx bit is
set (see the TCON register), a counter is incremented every falling edge
on T0 or T1 input pin. If not set, the TRx bit controls the corresponding
timer.
TMOD.6
TMOD.2
C/T
Selects Timer or Counter operation. When set to 1, the counter
operation is performed based on the falling edge of T0 or T1. When
cleared to 0, the corresponding register will function as a timer.
TMOD.5
TMOD.1
M1
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in
the TMOD description.
TMOD.4
TMOD.0
M0
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in
the TMOD description.
44
Rev. 1.2
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