參數(shù)資料
型號: 73S1209F-EB
廠商: Maxim Integrated Products
文件頁數(shù): 118/123頁
文件大?。?/td> 0K
描述: BOARD EVAL 73S1209F DOC/CD CABLE
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
主要目的: *
嵌入式: *
已用 IC / 零件: *
主要屬性: *
次要屬性: *
已供物品: 板,線纜,CD,電源
73S1209F Data Sheet
DS_1209F_004
Byte Control Register (SByteCtl): 0xFE12
0x2C
This register controls the processing of characters and the detection of the TS byte. When receiving, a
Break is asserted at 10.5 ETU after the beginning of the start bit. Break from the card is sampled at 11
ETU.
Table 90: The SByteCtl Register
MSB
LSB
DETTS
DIRTS
BRKDUR.1
BRKDUR.
0
Bit
Symbol
Function
SByteCtl.7
SByteCtl.6
DETTS
Detect TS Byte – 1 = Next Byte is TS, 0 = Next byte is not TS. When
set, the hardware will treat the next character received as the TS and
determine if direct or indirect convention is being used. Direct
convention is the default used if firmware does not set this bit prior to
transmission of TS by the smart card to the firmware. The hardware will
check parity and generate a break as defined by the DISPAR and
BRKGEN bits in the parity control register. This bit is cleared by
hardware after TS is received. TS is decoded before being stored in
the receive FIFO.
SByteCtl.5
DIRTS
Direct Mode TS Select – 1 = direct mode, 0 = indirect mode.
Set/cleared by hardware when TS is processed indicating either
direct/indirect mode of operation. When switching between smart
cards, the firmware should write the bit appropriately since this register
is not unique to an individual smart card (firmware should keep track of
this bit).
SByteCtl.4
BRKDUR.1
Break Duration Select – 00 = 1 ETU, 01 = 1.5 ETU, 10 = 2 ETU, 11 =
reserved. Determines the length of a Break signal which is generated
when detecting a parity error on a character reception in T=0 mode.
SByteCtl.3
BRKDUR.0
SByteCtl.2
SByteCtl.1
SByteCtl.0
94
Rev. 1.2
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