參數(shù)資料
型號: 73S1209F-EB
廠商: Maxim Integrated Products
文件頁數(shù): 116/123頁
文件大小: 0K
描述: BOARD EVAL 73S1209F DOC/CD CABLE
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
主要目的: *
嵌入式: *
已用 IC / 零件: *
主要屬性: *
次要屬性: *
已供物品: 板,線纜,CD,電源
73S1209F Data Sheet
DS_1209F_004
SC Clock Configuration Register (SCCLK): 0xFE0F
0x0C
This register controls the internal smart card (CLK) clock generation.
Table 87: The SCCLK Register
MSB
LSB
ICLKFS.5 ICLKFS.4 ICLKFS.3 ICLKFS.2 ICLKFS.1 ICLKFS.0
Bit
Symbol
Function
SCCLK.7
SCCLK.6
SCCLK.5
ICLKFS.5
Internal Smart Card CLK Frequency Select – Division factor to determine
internal smart card CLK frequency. MCLK clock is divided by (register
value + 1) to clock the ETU divider, and then by 2 to generate CLK. Default
ratio is 13. The programmed value in this register is applied to the divider
after this value is written, in such a manner as to produce a glitch-free
output, regardless of the selection of active interface. A register value = 0
will default to the same effect as register value = 1.
SCCLK.4
ICLKFS.4
SCCLK.3
ICLKFS.3
SCCLK.2
ICLKFS.2
SCCLK.1
ICLKFS.1
SCCLK.0
ICLKFS.0
External SC Clock Configuration Register (SCECLK): 0xFE10
0x0C
This register controls the external smart card (SCLK) clock generation.
Table 88: The SCECLK Register
MSB
LSB
ECLKFS.5
ECLKFS.4
ECLKFS.
3
ECLKFS.2 ECLKFS.1 ECLKFS.0
Bit
Symbol
Function
SCECLK.7
SCECLK.6
SCECLK.5
ECLKFS.5
External Smart Card CLK Frequency Select – Division factor to determine
external smart card CLK frequency. MCLK clock is divided by (register
value + 1) to clock the ETU divider, and then by 2 to generate SCLK.
Default ratio is 13. The programmed value in this register is applied to the
divider after this value is written, in such a manner as to produce a glitch-
free output, regardless of the selection of active interface. A register value
= 0 will default to the same effect as register value = 1.
SCECLK.4
ECLKFS.4
SCECLK.3
ECLKFS.3
SCECLK.2
ECLKFS.2
SCECLK.1
ECLKFS.1
SCECLK.0
ECLKFS.0
92
Rev. 1.2
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