
395
μPD780948, μPD78F0948, μPD780949, μPD78F0949
23.2.2 STOP mode
(1) STOP mode set and operating status
The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.
Cautions:
1. When the STOP mode is set, the X2 pin is internally connected to V
DD
via a pull-
up resistor to minimize leakage current at the crystal oscillator. Thus, do not use
the STOP mode in a system where an external clock is used for the main system
clock.
2. Because the interrupt request signal is used to clear the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag
reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset
to the HALT mode immediately after execution of the STOP instruction. After the
wait set using the oscillation stabilization time select register (OSTS), the operating
mode is set.
The operating status in the STOP mode is described below.
Table 23-3: STOP Mode Operating Status
STOP mode setting
With subsystem clock
Without subsystem clock
Item
Clock generator
CPU
Port (output latch)
16-bit timer /event counter (TM0)
16-bit timer (TM2)
8-bit timer event counter 5 and 6
Only main system clock stops oscillation
Operation stops
Status before STOP mode setting is held
Operable when TI is selected as count clock
Operation stops
Operable when TI50 or TI51 are selected as count clock
Operable when fxt is selected as
count clock
Operation stops
Operation stops
Operable at external SCK
Operation stops
Operation stops
Operable
Operation stops
Watch timer
Operation stops
Watchdog timer
A/D converter
Serial I/F
CAN
Sound generator
External interrupt (INTP0 to INTP4)
LCD
Bus lines in external expansion
AD0 to AD7
A8 to A15
ASTB
WR, RD
High impedance
Status before STOP mode is held
Low level
High level