
320
μPD780948, μPD78F0948, μPD780949, μPD78F0949
DEF
Redefine Permission Bit
0
Normal operation
1
Receive operation for selected message is disabled
CPU can change definition data for this message
SEL3
SEL2
SEL1
SEL0
Buffer selection (n =0...15)
0
0
0
0
Buffer 0 is selected for redefinition
0
0
0
1
Buffer 1 is selected for redefinition
0
0
1
0
Buffer 2 is selected for redefinition
0
0
1
1
Buffer 3 is selected for redefinition
0
1
0
0
Buffer 4 is selected for redefinition
0
1
0
1
Buffer 5 is selected for redefinition
0
1
1
0
Buffer 6 is selected for redefinition
0
1
1
1
Buffer 7 is selected for redefinition
1
0
0
0
Buffer 8 is selected for redefinition
1
0
0
1
Buffer 9 is selected for redefinition
1
0
1
0
Buffer 10 is selected for redefinition
1
0
1
1
Buffer 11 is selected for redefinition
1
1
0
0
Buffer 12 is selected for redefinition
1
1
0
1
Buffer 13 is selected for redefinition
1
1
1
0
Buffer 14 is selected for redefinition
1
1
1
1
Buffer 15 is selected for redefinition
Other than above
Setting prohibited
18.15.4 Special functions
Redefinition Control Register
These register controls redefinition of an identifier of a receive messages of the DCAN-module.
REDEF can be written with a 1-bit or an 8-bit memory manipulation instruction.
RESET input sets REDEF to 00H.
Figure 18-48: Redefinition Control Register
The redefinition register provides a way to change identifiers and other control information for one receive
buffer, without disturbing the operation of the other buffers.
This bit is cleared when INIT bit in CANC is set.
Cautions:
1. Do not change DEF and SEL at the same time. Change SEL only when DEF is cleared.
2. Write first SEL with DEF cleared. Write than SEL with DEF, or use bit manipulation
instruction.
3. Clear DEF but keeping SEL set to same value.
Symbol
ù
DEF
6
5
4
3
2
1
0
Address
After Reset
R/W
REDEF
0
0
0
SEL3
SEL2
SEL1
SEL0
FFB3H
00H
R/W