
369
μPD780948, μPD78F0948, μPD780949, μPD78F0949
21.4.2 Maskable interrupt request acknowledge operation
A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and
the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt
enable state (with IE flag set to 1). However, a low-priority interrupt request is not acknowledged during
high-priority interrupt service (with ISP flag reset to 0).
Wait times maskable interrupt request generation to interrupt servicing are as follows.
Table 21-3: Times from Maskable Interrupt Request Generation to Interrupt Service
Minimum Time
Maximum Time
Note
When xxPRx = 0
7 clocks
32 clocks
When xxPRx = 1
8 clocks
33 clocks
Note:
If an interrupt request is generated just before a divide instruction, the wait time is maximized.
Remark:
1 clock: (f
CPU
: CPU clock)
f
CPU
If two or more maskable interrupt requests are generated simultaneously, the request specified for higher
priority with the priority specify flag is acknowledged first. If two or more requests are specified for the
same priority with the priority specify flag, the interrupt request with the higher default priority is
acknowledged first.
Any reserved interrupt requests are acknowledged when they become acknowledgeable.
Figure 21-10 shows interrupt request acknowledge algorithms.
When a maskable interrupt request is acknowledged, the contents of program status word (PSW) and
program counter (PC) are saved to stacks, in this order. Then, the IE flag is reset (to 0), and the value
of the acknowledged interrupt priority specify flag is transferred to the ISP flag. Further, the vector table
data determined for each interrupt request is loaded into PC and branched.
Return from the interrupt is possible with the RETI instruction.