
215
μPD780948, μPD78F0948, μPD780949, μPD78F0949
13.4 A/D Converter Operations
13.4.1 Basic operations of A/D converter
<1>
Select one channel for A/D conversion with the analog input channel specification register (ADS1).
<2>
The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<3>
When sampling has been done for a certain time, the sample & hold circuit is placed in the hold
state and the input analog voltage is held until the A/D conversion operation is ended.
<4>
Set bit 7 of the successive approximation register (SAR) so that the tap selector sets the series
resistor string voltage tap to (1/2) AV
DD
.
<5>
The voltage difference between the series resistor string voltage tap and analog input is compared
with the voltage comparator. If the analog input is greater than (1/2) AV
DD
, the MSB of SAR remains
set. If the analog input is smaller than (1/2) AV
DD
, the MSB is reset.
<6>
Next, bit 6 of SAR is automatically set, and the operation proceeds to the next comparison. The
series resistor string voltage tap is selected according to the preset value of bit 7, as described
below.
Bit 7 = 1: (3/4) AV
DD
Bit 7 = 0: (1/4) AV
DD
The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated as follows.
Analog input voltage
≥
Voltage tap: Bit 6 = 1
Analog input voltage < Voltage tap: Bit 6 = 0
<7>
Comparison is continued in this way up to bit 0 of SAR.
<8>
Upon completion of the comparison of 8 bits, an effective digital result value remains in SAR, and
the result value is transferred to and latched in the A/D conversion result register (ADCR1).
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
Caution:
The first A/D conversion value just after A/D conversion is undefined.