
301
μPD780948, μPD78F0948, μPD780949, μPD78F0949
INIT
Initialize
0
Normal operation
1
Initialization mode
18.13
18.13.1 Status register
CAN
CAN Control Register
These register sets the CAN control definition of the CAN module.
CANC can be set with a 1-bit or an 8-bit memory manipulation instruction.
RESET input sets CANC to 01H.
Figure 18-33: CAN Control Register
RxF and TxF are read only bits.
INIT is used configure savely all bus and compare parameters, without creating unsolicited behaviour.
INIT initiates the DCAN to set all internal activities to inactive states. Due to actual bus protocol activities
this may need some time. The actual status is shown in the INITSTATE bit in the CANES register.
The CTxD output stays recessive (logical high) during this initialization.
Changing of the following registers is only permitted when INIT is active:
MCNT, SYNC0, SYNC1, MASKC.
Any write to these registers when INIT = 0 is ignored.
The clock supply to the DCAN is switched off during sleep and stop condition of the DCAN.
The sleep condition is cleared under following conditions:
a) CPU clears the SLEEP bit.
b) Transition on CAN Bus. Only when STOP = 0.
c) CPU sets SLEEP, but CAN protocol is active due to bus activity.
The WAKE bit in CANES is set under condition b) and c). An error interrupt is activated at the same time.
Symbol
7
6
5
÷
3
1
INIT
Address
After Reset
R/W
CANC
RxF
TxF
0
SOFE
SOFSEL
SLEEP
STOP
FFB0H
01h
R/W
SLEEP
Sleep/Stop Request for CAN protocol
0
Normal operation
1
CAN protocol goes to sleep or stop mode depending on STOP bit
STOP
Stop Mode Selection
0
Normal sleep operation / Sleep mode is released when a transition on
the CAN bus is detected
1
Stop operation / Sleep mode is cancelled only by CPU access. No
wake up from CAN bus