
315
μPD780948, μPD78F0948, μPD780949, μPD78F0949
TXAn
Transmission Abort Flag
0
Write: normal operation
Read: no abort pending
1
Write: aborts current transmission request for this buffer n
Read: abort is pending
TXCn
Transmission Complete Flag
0
Transmit was aborted / no data sent
1
Transmit was complete / abort had no effect
18.15
Function Control
18.15.1 Transmit control
Transmit Control Register
This register controls the transmission of the DCAN-module. The Transmit Control register provides
complete control over the two transmit buffers and their status. It is possible to request and abort
transmission of both buffers independently.
TCR can be set with a an 8-bit memory manipulation instruction.
RESET input sets TCR to 00H.
Figure 18-45: Transmit Control Register
The user defines which buffer has to be send first in the case of both request bits are set. If only buffer
is requested, TXP has no influence.
This bit is checked by the DCAN immediately before the frame is started. The order in which the
TXRQ1/0 bits will be set does not influence as long as the first requested frame is not started on the
bus.
Setting the TXAn bit by the CPU request the CAN to free this buffer.
The TXAn bits have dual function:
1. The CPU can request an abort by writing a “1” into the bit.
2. The DCAN signals whether such an request is still pending. The bit is cleared at the same time when
the TXRQn is cleared.
This abort does not affect any rules of the CAN protocol. An already started frame will continue to its end.
Symbol
7
6
5
4
3
2
1
0
Address
After Reset
R/W
TCR
TXP
0
TXC1
TXC0
TXA1
TXA0
TXRQ1
TXRQ0
FFB1H
00H
R/W
TXP
Transmission Priority
0
Buffer 0 has priority over buffer 1
1
Buffer 1 has priority over buffer 0
TXC1 and TXC0 are read only bits.