
318
μPD780948, μPD78F0948, μPD780949, μPD78F0949
Symbol
7
6
5
4
3
2
1
0
Address
After Reset
R/W
MASKC
0
0
0
0
0
GLOBAL
MSK1
MSK0
FFBBH
00H
R/W
MSK0
Mask 0 Enable
0
Rec. buffer 0 and 1 in normal operation
1
Rec. buffer 0 is mask for buffer 1
MSK1
Mask 1 Enable
0
Rec. buffer 2 and 3 in normal operation
1
Rec. buffer 2 is mask for buffer 3
GLOBAL
Enable Global Mask
0
Normal mask operation
1
Highest defined mask is active for all following buffers
18.15.3 Mask control
The mask Control Register defines whether the DCAN compares the identifier of a received message
in its whole length or some bits are not used for comparison.
This functionality is provided by the use of mask information. The mask information defines for each bit
of the identifier whether it is used for comparison or not.
The DCAN uses a receive buffer for this information, when it is enabled in this register. This buffer is
not used for normal message storage then.
Mask Control Register
These register controls the mask function of the receive messages of the DCAN-module.
MASKC can be written with an 8-bit memory manipulation instruction.
RESET input sets MASKC to 00H.
Figure 18-47: Mask Control Register
This register is readable at any time. Write is only permitted when the CAN is in initialization mode.