- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376463 > XRT83SL30 (Exar Corporation) SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PDF資料下載
參數(shù)資料
| 型號： | XRT83SL30 |
| 廠商： | Exar Corporation |
| 英文描述： | SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | 單通道的T1/E1/J1上海收發(fā)器時鐘恢復(fù)和抖動衰減器 |
| 文件頁數(shù)： | 8/76頁 |
| 文件大小： | 376K |
| 代理商： | XRT83SL30 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.4
á
PRELIMINARY
5
RECEIVER
S
IGNAL
N
AME
P
IN
#
T
YPE
D
ESCRIPTION
RLOS
63
O
Receiver Loss of Signal
This signal is asserted ‘High’ for at least one RCLK cycle to indicate loss of
signal at the receive input. RLOS will remain “High” for the entire duration of
the loss of signal detected by the receiver logic.
RCLK
64
O
Receiver Clock Output
RNEG
LCV
1
O
Receiver Negative Data Output
In dual-rail mode, this signal is the receiver negative-rail output data.
Line Code Violation Output
In single-rail mode, this signal goes ‘High’ for one RCLK cycle to indicate a
code violation is detected in the received data. If AMI coding is selected,
every bipolar violation received will cause this pin to go “High”.
RPOS
RDATA
2
O
Receiver Positive Data Output
In dual-rail mode, this signal is the receive positive-rail output data sent to the
Framer.
Receiver NRZ Data Output
In single-rail mode, this signal is the receive NRZ format output data sent to
the Framer.
RTIP
4
I
Receiver Differential Tip Positive Input
Positive differential receive input from the line.
RRING
5
I
Receiver Differential Ring Negative Input
Negative differential receive input from the line.
RXMUTE
50
I
Receive Muting
In
Hardware Mode
, connect this pin ‘High’ to mute RPOS and RNEG out-
puts to a “Low” state upon receipt of LOS condition to prevent data chatter-
ing. Connect this pin to ‘Low’ to disable muting function.
N
OTE
:
Internally pulled “Low” with 50k
resistor.
RCLKE
53
I
Receive Clock Edge
In
Hardware Mode
, with this pin set to ‘High’ the output receive data is
updated on the falling edge of RCLK. With this pin tied ‘Low’, output data is
updated on the rising edge of RCLK.
N
OTE
:
Internally pulled “Low” with a 50k
resistor.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT83SL30IV | SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83VSH28 | 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83VSH28IB | 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83VSH314 | 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83VSH314IB | 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83SL30ES | 功能描述:外圍驅(qū)動器與原件 - PCI 1 CHT1/E1 LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83SL30IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83SL30IV-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT83SL30IVTR-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83SL314 | 制造商:EXAR 制造商全稱:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。