參數(shù)資料
型號(hào)： XRT83SL30
廠商： Exar Corporation
英文描述： SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： 單通道的T1/E1/J1上海收發(fā)器時(shí)鐘恢復(fù)和抖動(dòng)衰減器
文件頁(yè)數(shù)： 44/76頁(yè)
文件大?。?/td> 376K
代理商： XRT83SL30
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.4
Bit 2 through 6:The five (5) Address Values (labeled A0, A1, A2, A3 and A4)
The next five rising edges of the SCLK signal, clock in the 5-bit address value for the Read or Write operation.
These five bits define the register address within XRT83SL30 that the user has selected to read data from or
write data to. The address bits must be supplied to the SDI input in ascending order with LSB (Least Significant
Bit) first.
Bit 7:
(A5)
The next bit A5 must be set to “0” as shown in Figure 23.
Bit 8:
(A6)
The value of A6 is a “don’t care”.
Once the first eight bits have been written into the Serial interface, the subsequent action depends on the
whether the current operation is a “Read” or “Write” instruction.
Read Operation
With the last address bit “A4” written into the SDI input, the “Read” operation will proceed through an idle peri-
od lasting two SCLK periods. On the rising edge of the 9th SCLK the serial data output (SDO) becomes active
(see Figure 23). At this point the user can begin reading the 8-bit data (D0 through D7) stored in the interface
register at address [A4,A3,A2,A1,A0], in ascending order (LSB first), on the falling edge of SCLK.
Write Operation
With the last address bit (A4) written into the SDI input, the “Write” operation will proceed through an idle peri-
od lasting two SCLK periods. Prior to the rising edge of the 9th SCLK, the user must begin to apply the eight bit
data word to the SDI input. The Serial Interface will latch this data on the rising edge of SCLK. The serial data
(D0 through D7) should enter the SDI input in ascending order with the LSB first.
Serial Interface Register Description
The serial Interface consists of 32 8-bit register locations. The Microprocessor register address map and Bit
map are described in Table 16 and Table 17 respectively. The function of the individual bits are described in
Table 18 through Table 36.
á
PRELIMINARY
41
F
IGURE
23. M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
D
ATA
S
TRUCTURE
5
6
7
8
1
2
3
4
13
14
15
16
9
10
11
12
R/W
Ao
A1
A2
A3
A4
0
A6
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
CS
SCLK
SDI
SDO
High Z
High Z
相關(guān)PDF資料
PDF描述
XRT83SL30IV SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
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XRT83VSH28IB 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
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XRT83VSH314IB 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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參數(shù)描述
XRT83SL30ES 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 1 CHT1/E1 LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83SL30IV 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
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XRT83SL314 制造商:EXAR 制造商全稱:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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