參數(shù)資料
型號(hào): XRT83SL30
廠商: Exar Corporation
英文描述: SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述: 單通道的T1/E1/J1上海收發(fā)器時(shí)鐘恢復(fù)和抖動(dòng)衰減器
文件頁(yè)數(shù): 21/76頁(yè)
文件大?。?/td> 376K
代理商: XRT83SL30
á
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.4
18
In
Host
mode the programming is achieved through the corresponding interface control bits, the state of the
CLKSEL[2:0] control bits and the state of the MCLKRATE interface control bit.
RECEIVER
RECEIVER INPUT
At the receiver input, a cable attenuated AMI signal can be coupled to the receiver through a capacitor or a 1:1
transformer. The input signal is first applied to a selective equalizer for signal conditioning. The maximum
equalizer gain is up to 15dB for T1 and E1 modes. The equalized signal is subsequently applied to a peak
detector which in turn controls the equalizer settings and the data slicer. The slicer threshold for both E1 and
T1 is typically set at 50% of the peak amplitude at the equalizer output. After the slicers, the digital
representation of the AMI signals are applied to the clock and data recovery circuit. The recovered data
subsequently goes through the jitter attenuator and decoder (if selected) for HDB3 or B8ZS decoding before
being applied to the RPOS/RDATA and RNEG/LCV pins. Clock recovery is accomplished by a digital phase-
locked loop (DPLL) which does not require any external components and can tolerate high levels of input jitter
that meets or exceeds the ITU-G.823 and TR-TSY000499 standards.
In
Hardware
mode only, this receive channel is turned on upon power-up and is always on. In
Host
mode, the
receiver can be turned on or off with the RXON bit.
See “Microprocessor Register #2 bit description” on
page 47.
T
ABLE
1: M
ASTER
C
LOCK
G
ENERATOR
MCLKE1
K
H
Z
MCLKT1
K
H
Z
CLKSEL2
CLKSEL1
CLKSEL0
MCLKRATE
M
ASTER
C
LOCK
K
H
Z
2048
2048
0
0
0
0
2048
2048
2048
0
0
0
1
1544
2048
1544
0
0
0
0
2048
1544
1544
0
0
1
1
1544
1544
1544
0
0
1
0
2048
2048
1544
0
0
1
1
1544
8
x
0
1
0
0
2048
8
x
0
1
0
1
1544
16
x
0
1
1
0
2048
16
x
0
1
1
1
1544
56
x
1
0
0
0
2048
56
x
1
0
0
1
1544
64
x
1
0
1
0
2048
64
x
1
0
1
1
1544
128
x
1
1
0
0
2048
128
x
1
1
0
1
1544
256
x
1
1
1
0
2048
256
x
1
1
1
1
1544
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