參數(shù)資料
型號： XRT83SL30
廠商： Exar Corporation
英文描述： SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： 單通道的T1/E1/J1上海收發(fā)器時鐘恢復(fù)和抖動衰減器
文件頁數(shù)： 25/76頁
文件大小： 376K
代理商： XRT83SL30
á
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
ARBITRARY PULSE GENERATOR
REV. P1.0.4
22
In T1 mode only, the arbitrary pulse generator divides the pulse into eight individual segments. Each segment
is set by a 7-Bit binary word by programming the appropriate register. This allows the system designer to set
the overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit
is set to “1”, the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is
set to “0”, the segment will move in a negative direction relative to a flat line condition. A pulse with numbered
segments is shown in Figure 9.
N
OTE
:
By default, the arbitrary segments are programmed to 0x00h. The transmitter output will result in an all zero pattern
to the line.
TRANSMITTER
DIGITAL DATA FORMAT
Both the transmitter and receiver can be configured to operate in dual or single-rail data formats. This feature is
available under both
Hardware
and
Host
control modes. The dual or single-rail data format is determined by
the state of the SR/DR pin in
Hardware
mode or SR/DR interface bit in the
Host
mode. In single-rail mode,
transmit clock and NRZ data are applied to TCLK and TPOS/TDATA pins respectively. In single-rail and
Hardware
mode the TNEG/CODE input can be used as the CODES function. With TNEG/CODE tied “Low”,
HDB3 or B8ZS encoding and decoding are enabled for E1 and T1 modes respectively. With TNEG/CODE tied
“High”, the AMI coding scheme is selected. In both dual or single-rail modes of operations, the transmitter
converts digital input data to a bipolar format before being transmitted to the line.
TRANSMIT CLOCK (TCLK) SAMPLING EDGE
Serial transmit data at TPOS/TDATA and TNEG/CODE are clocked into the XRT83SL30 under the
synchronization of TCLK. With a “0” written to the TCLKE interface bit, or by pulling the TCLKE pin “Low”, input
data is sampled on the falling edge of TCLK. The sampling edge is inverted with a “1” written to TCLKE
interface bit, or by connecting the TCLKE pin “High”.
F
IGURE
9. A
RBITRARY
P
ULSE
S
EGMENT
A
SSIGNMENT
1
2
3
4
5
6
7
8
Segment
Register
1
2
3
4
5
6
7
8
0xn8
0xn9
0xna
0xnb
0xnc
0xnd
0xne
0xnf
相關(guān)PDF資料
PDF描述
XRT83SL30IV SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH28IB 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH314IB 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT83SL30ES 功能描述:外圍驅(qū)動器與原件 - PCI 1 CHT1/E1 LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83SL30IV 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XRT83SL30IV-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT83SL30IVTR-F 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83SL314 制造商:EXAR 制造商全稱:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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