
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.4
á
PRELIMINARY
2
FEATURES
Fully integrated single-channel short-haul trans-
ceiver for E1,T1 or J1 applications
Programmable Transmit Pulse Shaper for E1,T1 or
J1 short-haul interfaces
Five fixed transmit pulse settings for T1 short-haul
applications plus a fully programmable waveform
generator for transmit output pulse shaping
High receiver interference immunity
Receive monitor mode handles 0 to 29dB resistive
attenuation along with 0 to 6dB of cable attenuation
for both T1 and E1 modes
Supports 75
and 120
(E1), 100
(T1) and 110
(J1) applications.
Internal and/or external impedance matching for
75
,100
,
110
and 120
.
Tri-State transmit output and receive input capabil-
ity for redundancy applications
Provides High Impedance for Tx and Rx during
power off
Transmit return loss meets or exceeds ETSI 300
166 standard
On-chip digital clock recovery circuit for high input
jitter tolerance
Crystal-less digital jitter attenuator with 32-bit or 64-
bit FIFO Selectable either in transmit or receive
path
On-chip frequency multiplier generates T1 or E1
Master clocks from variety of external clock sources
On-chip transmit short-circuit protection and limit-
ing, and driver fail monitor output (DMO)
Receive loss of signal (RLOS) output
On-chip HDB3/B8ZS/AMI encoder/decoder
QRSS pattern generation and detection for testing
and monitoring
Error and Bipolar Violation Insertion and Detection
Receiver Line Attenuation Indication Output in 1dB
steps
Network Loop-Code Detection for automatic Loop-
Back Activation/Deactivation
Transmit All Ones (TAOS) and In-Band Network
Loop Up and Down code generators
Supports Local Analog, Remote, Digital and Dual
Loop-Back Modes
Meets or exceeds T1 and E1 short-haul network
access specifications in ITU G.703, G.775, G.736
and G.823; TR-TSY-000499; ANSI T1.403 and
T1.408; ETSI 300-166 and AT&T Pub 62411
Supports both Hardware and serial Microprocessor
interface for programming
F
IGURE
2. B
LOCK
D
IAGRAM
OF
THE
XRT83SL30 T1/E1/J1 LIU (H
ARDWARE
M
ODE
)
HW/HOST
GAUGE
JASEL1
JASEL0
RXTSEL
TXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
ICT
JABW
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS
MCLKE1
MCLKT1
CLKSEL[2:0]
TXTEST[0:2]
INSBPV
TPOS / TDATA
TNEG / CODES
TCLK
QRPD
RCLK
RNEG / LCV
RPOS / RDATA
NLCD
RLOS
RTIP
RRING
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
DMO
TTIP
TRING
TXON
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
LOCAL
ANALOG
LOOPBACK
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
RX
EQUALIZER
EQUALIZER
CONTROL
AIS
DETECTOR
LOS
DETECTOR
LBO[3:0]
LOOPBACK
ENABLE
J
S
NLCD ENABLE
QRSS ENABLE
HARWARE CONTROL
TEST
DRIVE
MONITOR
DFM
MCLKOUT
LOOP1
LOOP0
AISD
TAOS
ENABLE