R
參數(shù)資料
型號(hào)： XRT83L34IV-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 98/99頁(yè)
文件大小： 0K
描述： IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝： 72
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
其它名稱： XRT83L34IV-F-ND
XRT83L34
xr
REV. 1.0.1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
95
REVISIONS
REVISION
DESCRIPTION
A1.0.1
thru
A1.0.7
Advanced Versions
P1.1.0
Preliminary release version
P1.2.0
Added GHCI_n, SL_1, SL_0, EQG_1 and EQG_0 to Control Global Register 131. Separated Micropro-
cessor description table by register number. Moved absolute maximum and Dc electrical characteristics
before AC electrical characteristics. Replaced TBD’s in electrical ables. Reformated table of contents.
P1.2.1
Added GAUGE1 and GAUGE0 to Control Global Register 131. Corrected control register binary bits.
P1.2.2
Renamed FIFO pin to GAUGE, edited definition and edited defintion of JASEL[1:0] to reflect the FIFO
size is selected by the jitter attenuator select.
P1.2.3
Redefined bits D3, D2 and D0 of register 1, in combination these bits set the jitter attenuator path and
FIFO size.
P1.2.4
Corrected typos in figures 6 and 8. Added Jitter attenuator tables in microprocessor register tables. Mod-
ified microprocessor descrptions, timing diagrams and electrical characteristics.
P1.2.5
Replaced GCHIE with Reserved in Tables 18, 23, 24,25. In the pin list description for INT, replace IMASK
bit to a “1” with GIE bit to a “0”.
P1.2.6
New description for bits D6 - D0 in Tables 27 - 34 Microprocessor Registers.
P1.2.7
Revised Microprocessor interface timing diagrams and data.
P1.2.8
Corrected microprocessor timing information and edited Redundancy section.
P1.2.9
Edited section on RLOS for more detailed explanation.
P1.3.0
Changed definition of TXON_n pin. RXON_n bit included in register tables. Rx transformer ratio changed
from 2:1 to 1:1. Description of Arbitrary Pulse and Gap Clock support added.
P1.3.1
Minor edits to block diagram, changed issue date to January, corrected register 67 in table 18, corrected
table 37.
P1.3.2
Swapped the function of PTS1 and PTS2. Replaced Processor timing diagrams and timing informa-
tion, (Figures 29 and 30 -- Tables 49 and 50).
P1.3.3
Updated the Power Consumption numbers.
P1.3.4
Added the New E1 Arbitrary Pulse Feature. Added descriptions to the global registers.
1.0.0
Final Release.
1.0.1
Added Microprocessor Section. Removed Sychronous Microprocessor modes.
相關(guān)PDF資料
PDF描述
XRT83L38IB-F IC LIU T1/E1/J1 OCTAL 225BGA
XRT83SH314IB-F IC LIU T1/E1/J1 14CH 304TBGA
XRT83SH38IB-F IC LIU SH T1/E1/J1 8CH 225BGA
XRT86L30IV-F IC LIU/FRAMER TI/E1/J1 SGL 128LQ
XRT86VL30IV-F IC FRAMR/LIU T1/E1/J1 QD 128LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT83L34IVTR 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83L34IVTR-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83L38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XRT83L38_07 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XRT83L38ES 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*