QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 64
參數(shù)資料
型號: XRT83L34IV-F
廠商: Exar Corporation
文件頁數(shù): 64/99頁
文件大小: 0K
描述: IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝: 72
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 4/4
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
其它名稱: XRT83L34IV-F-ND
xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
64
TABLE 21: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION
REGISTER ADDRESS
0000001
0010001
0100001
0110001
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
RXTSEL_n
Receiver Termination Select: In Host mode, this bit is used
to select between the internal and external line termination
modes for the receiver according to the following table;
R/W
0
D6
TXTSEL_n
Transmit Termination Select: In Host mode, this bit is used
to select between the internal and external line termination
modes for the transmitter according to the following table;
R/W
0
D5
TERSEL1_n
Termination Impedance Select1:
In Host mode and in internal termination mode, (TXTSEL = “1”
and RXTSEL = “1”) TERSEL[1:0] control the transmit and
receive termination impedance according to the following
table;
In the internal termination mode, the receiver termination of
each receiver is realized completely by internal resistors or by
the combination of internal and one fixed external resistor.
In the internal termination mode, the transmitter output should
be AC coupled to the transformer.
R/W
0
D4
TERSEL0_n
Termination Impedance Select bit 0:
See description of bit D5 for the function of this bit.
R/W
0
RXTSEL
RX Termination
0
1
External
Internal
TXTSEL
TX Termination
0
1
External
Internal
TERSEL1 TERSEL0
0
1
0
1
Termination
100
110
75
120
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