QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 60 MIC" />
參數(shù)資料
型號(hào)： XRT83L34IV-F
廠商： Exar Corporation
文件頁數(shù)： 60/99頁
文件大小： 0K
描述： IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝： 72
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
其它名稱： XRT83L34IV-F-ND
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XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
60
MICROPROCESSOR REGISTER TABLES
The microprocessor interface consists of 256 addressable locations. Each channel uses 16 dedicated 7 bit
registers for independent programming and control. There are four additional registers for global control of all
channels and two registers for device identification and revision numbers. The remaining registers are for
factory test and future expansion. The control register map and the function of the individual bits are
summarized in Table 18 and Table 19 respectively.
TABLE 18: MICROPROCESSOR REGISTER ADDRESS
REGISTER NUMBER
REGISTER ADDRESS
FUNCTION
HEX
BINARY
0 - 15
0x00 - 0x0F
0000000 - 0001111
Channel 0 Control Registers
16 - 31
0x10 -0x1F
0010000 - 0011111
Channel 1 Control Registers
32 - 47
0x20 - 0x2F
0100000 - 0101111
Channel 2 Control Registers
48 - 63
0x30 - 0x3F
0110000 - 0111111
Channel 3 Control Registers
64 - 67
0x40 - 0x43
1000000 - 1000011
Command Control Registers for All 4 Channels
68 - 75
0x44 - 0x4B
1000100 - 1001011
R/W registers reserved for testing purpose.
76-125
0x4C - 0x7D
1001100 - 1111101
Reserved
126
0x7E
1111110
Device ID
127
0x7F
1111111
Device Revision ID
TABLE 19: MICROPROCESSOR REGISTER BIT DESCRIPTION
REG. #
ADDRESS
REG.
TYPE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Channel 0 Control Registers
0
0000000
Hex 0x00
R/W
Reserved
RXON_n
EQC4_n
EQC3_n
EQC2_n
EQC1_n
EQC0_n
1
0000001
Hex 0x01
R/W
RXTSEL_n
TXTSEL_n
TERSEL1_n
TERSEL0_n
JASEL1_n
JASEL0_n
JABW_n
FIFOS_n
2
0000010
Hex 0x02
R/W
INVQRSS_n
TXTEST2_n
TXTEST1_n
TXTEST0_n
TXON_n
LOOP2_n
LOOP1_n
LOOP0_n
3
0000011
Hex 0x03
R/W
NLCDE1_n
NLCDE0_n
CODES_n
RXRES1_n
RXRES0_n
INSBPV_n
INSBER_n
TRATIO_n
4
0000100
Hex 0x04
R/W
Reserved
DMOIE_n
FLSIE_n
LCVIE_n
NLCDIE_n
AISDIE_n
RLOSIE_n
QRPDIE_n
5
0000101
Hex 0x05
RO
Reserved
DMO_n
FLS_n
LCV_n
NLCD_n
AISD_n
RLOS_n
QRPD_n
6
0000110
Hex 0x06
RUR
Reserved
DMOIS_n
FLSIS_n
LCVIS_n
NLCDIS_n
AISDIS_n
RLOSIS_n
QRPDIS_n
7
0000111
Hex 0x07
RO
Reserved
CLOS5_n
CLOS4_n
CLOS3_n
CLOS2_n
CLOS1_n
CLOS0_n
8
0001000
Hex 0x08
R/W
X
B6S1_n
B5S1_n
B4S1_n
B3S1_n
B2S1_n
B1S1_n
B0S1_n
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