參數(shù)資料
型號: XRT83L34IV-F
廠商: Exar Corporation
文件頁數(shù): 65/99頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 QUAD 128TQFP
標準包裝: 72
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 4/4
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設備封裝: 128-TQFP(14x20)
包裝: 托盤
其它名稱: XRT83L34IV-F-ND
XRT83L34
xr
REV. 1.0.1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
65
D3
JASEL1_n
Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits
are used to disable or place the jitter attenuator of each chan-
nel independently in the transmit or receive path.
R/W
0
D2
JASEL0_n
Jitter Attenuator select bit 0: See description of bit D3 for the
function of this bit.
R/W
0
D1
JABW_n
Jitter Attenuator Bandwidth Select: In E1 mode, set this bit
to “1” to select a 1.5Hz Bandwidth for the Jitter Attenuator. The
FIFO length will be automatically set to 64 bits. Set this bit to
“0” to select 10Hz Bandwidth for the Jitter Attenuator in E1
mode. In T1 mode the Jitter Attenuator Bandwidth is perma-
nently set to 3Hz, and the state of this bit has no effect on the
Bandwidth.
R/W
0
D0
FIFOS_n
FIFO Size Select: See table of bit D1 above for the function of
this bit.
R/W
0
TABLE 21: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION
JASEL1
bit D3
JASEL0
bit D2
0
1
0
1
JA Path
JA Disabled
JA in Transmit Path
JA in Receive Path
0
1
0
1
0
1
0
1
FIFOS_n
bit D0
0
1
0
1
JABW
bit D1
T1
E1
Mode
32
64
32
64
32
64
FIFO
Size
3
10
1.5
JA B-W
Hz
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