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參數(shù)資料
| 型號： | XRT83L34IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 55/99頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | XRT83L34IV-F-ND |
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XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
56
TABLE _, THE ROLES OF VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO
OPERATE IN THE MOTOROLA-ASYNCHRONOUS MODE
PIN
NAME
PIN NUMBER
TYPE
DESCRIPTION
ALE/AS
71
I
Address Strobe Input - AS*:
If the Microprocessor Interface has been configured to operate in the
Motorola-Asynchronous Mode, then pulling this input pin "LOW enables
the "input" bus drivers for the Address Bus Input pins.
During each READ or WRITE operation, the user is expected to drive
this input pin "LOW" after (or around the time that) he/she has places the
address (of the "target" register) onto the Address Bus pins (A[6:0]). The
user is then expected to hold this input pin "LOW" for the remainder of
the READ or WRITE cycle.
NOTE: It is permissible to tie the ALE_AS* and CS* input pins together..
Read and Write operations will be performed properly if ALE_AS
is driven "LOW" coincident to whenever CS* is also driven
"LOW".
RD*/DS*
70
I
Data Strobe Input - RD*:
If the MIcroprocessor Interface is operating in the Motorola-Asynchro-
nous Mode, then this input pin will function as the DS* (Data Strobe)
Input signal.
RDY*/
DTACK
73
O
Data Transfer Acknowledge Output - DTACK*:
If the Microprocessor Interface has been configured to operate in the
Motorola-Asynchronous Mode, then this output pin will function as the
"active-low" DTACK Output.
During a READ or WRITE cycle, the Microprocessor Interface block will
toggle this output pin to the logic low level, ONLY when it (the Micropro-
cessor Interface) is ready to complete or terminate the current READ or
WRITE cycle. Once the Microprocessor has determined that this input
pin has toggled to the logic "LOW" level, then it is now safe for it to move
on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface block is
output pin at a logic "HIGH" level, then the Microprocessor is expected to
extend this READ or WRITE cycle, until it detects this output pin being
toggled to the logic "LOW" level.
WR*/
R/W*
69
I
Read/Write Operation Identification Input - R/W*:
If the Microprocessor Interface is operating in the "Motorola-Asynchro-
nous" Mode, then this pin is functionally equivalent to the R/W* input pin.
In the Motorola Mode, a READ operation occurs if this pin is held at a
logic "1" level, coincident to a falling edge of the RD/DS* (Data Strobe)
input pin. Similarly, a WRITE operation occurs if this pin is at a logic "0"
level, coincident to a falling edge of the RD/DS* (Data Strobe) input pin.
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