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參數(shù)資料
| 型號： | XRT83L34IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 58/99頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | XRT83L34IV-F-ND |
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xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
58
Asynchronous" READ Operation.
THE MOTOROLA-ASYNCHRONOUS WRITE CYCLE
If the Microprocessor Interface (of the XRT83L34 device) has been configured to operate in the Motorola-
Asynchronous Mode, then the Microprocessor should do all of the following, anytime it wishes to write a byte of
data into a register within the XRT83L34 device.
1. Place the address of the "target" register within the XRT83L34 device, on the Address Bus input pins,
A[6:0].
2. While the Microprocessor is placing the address value on the Address Bus, the Address Decoding circuitry
(within the user’s system) should assert the CS* (Chip Select) input pin of the XRT83L34 device, by tog-
gling it "LOW". This action enables further communication between the Microprocessor and the XRT83L34
Microprocessor Interface.
3. Assert the ALE/AS (Address Strobe) input pin by toggling it "LOW". This step enables the "Address Bus"
input drivers, within the Microprocessor Interface block of the XRT83L34 device.
4. Afterwards, the Microprocessor Interface should indicate that this current bus cycle is a "WRITE" operation
by toggling the WR*/R/W* (R/W*) input pin "LOW".
5. The Microprocessor should then place the byte or word that it intends to write into the "target" register, on
the bi-direction data bus, D[7:0].
6. Next, the Microprocessor should initiate the bus cycle by toggling the RD*/DS* (Data Strobe) input pin
"LOW". When the XRT83L34 device senses that the WR/R/W* (R/W*) input pin is "HIGH" and that the
RD*/DS* (Data Strobe) input pin has toggled "LOW", it will enable the "input drivers" of the bi-directional
data bus, D[7:0].
7. Immediately after the Microprocessor toggles the RD*/DS* (Data Strobe) signal "LOW", the XRT83L34
device will continue to drive the "RDY*/DTACK* output pin "HIGH". The XRT83L34 device does this in
order to inform the Microprocessor that the data (to be written into the "target" address location, within the
XRT83L34 device) is "NOT READY" to be latched into the Microprocessor Interface circuitry (within the
XRT83L34 device). In this case, the Microprocessor should continue to hold the "Data Strobe" (RD*/DS*)
input pin "LOW" until it detects the "RDY*/DTACK* output pin toggling "HIGH".
FIGURE 27. ILLLUSTRATION OF A MOTOROLA-ASYNCHRONOUS MODE READ OPERATION
ALE/AS
RD*/DS*
A[6:0]
CS*
D[7:0]
RDY/DTACK*
Not Valid
Valid Data
Address of Target Register
WR*/R/W*
Microprocessor places “target”
Address value on A[6:0]
Address Decoding
Circuitry asserts
CS*
Microprocessor keeps R/W* “high”
To denote READ Operation
Read Operation begins
Here
DTACK* toggles “l(fā)ow” to indicate
That valid data can be read from
D[7:0]
Read Operation is
Terminated Here
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| XRT83L34IVTR | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L34IVTR-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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| XRT83L38ES | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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