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參數(shù)資料
| 型號： | XRT83L34IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 82/99頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 標準包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | XRT83L34IV-F-ND |
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xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
80
CLOCK SELECT REGISTER
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits and
the Master Clock Rate in register 0x41h. Therefore, if the clock selection bits or the MCLRATE bit are being
programmed, the frequency of the PLL output will be adjusted accordingly. During this adjustment, it is
important to "Not" write to any other bit location within the same register while selecting the input/output clock
frequency. For best results, whenever the user is changing bits D[6:3] (within the Clock Select Register), he/
she should execute a "Masked-Write" Operation, such that he/she will not change the remaining bits within this
register (e.g., D[7] and D[2:0] as shown below in Figure 29).
FIGURE 29. REGISTER 0X81H SUB REGISTERS
Programming Examples:
Example 1: Changing bits D[6:3]
If bits D[6:3] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 2: Changing bits D[7] and D[2:0]
If bits D[7] and D[2:0] are the only values within the register that will change in a WRITE process, the
microprocessor only needs to initiate ONE write operation.
Example 3: Changing bits within D[6:3] and the other bits
In this scenario, one must initiate TWO write operations such that bits D[6:3] and the other bits do not change
within ONE write cycle. It is recommended that bits D[6:0] and the other bits be treated as two independent
sub-registers. One can either change the clock selection bits and then change bits D[7] and D[2:0] on the
SECOND write, or vice-versa. No order or sequence is necessary.
D0
D1
D2
D3
D4
D5
D6
D7
Clock Selection Bits
ExLOS, ICT
E1arben
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83L34IVTR | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L34IVTR-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38ES | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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