QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 24 TER" />
參數(shù)資料
型號(hào)： XRT83L34IV-F
廠商： Exar Corporation
文件頁數(shù)： 20/99頁
文件大小： 0K
描述： IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝： 72
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
其它名稱： XRT83L34IV-F-ND
xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
24
TERSEL0
TERSEL1
113
112
I
Termination Impedance Select pin 0
Termination Impedance Select pin 1
In the Hardware mode and in the internal termination mode (TXTSEL=”1”
and RXTSEL=”1”), TERSEL[1:0] control the transmit and receive termination
impedance according to the following table.
In the internal termination mode, the receiver termination of each receiver
is realized completely by internal resistors or by the combination of internal
and one fixed external resistor (see description of RXRES[1:0] pins).
In the internal termination mode the transformer ratio of 1:2 and 1:1 is
required for transmitter and receiver respectively with the transmitter output
AC coupled to the transformer.
NOTES:
1.
This pin is internally pulled "Low" with a 50k
resistor.
2.
In Hardware Mode all channels share the same TERSEL control
function.
ICT
120
I
In-Circuit Testing (active "Low"):
When this pin is tied “Low”, all output pins are forced to a “High” impedance
state for in-circuit testing.
Pulling RESET and ICT pins “Low” simultaneously will put the chip in factory
test mode. For normal operation, the user should either leave this input pin
"floating" or pull it to a logic "HIGH" level.
NOTE: Internally pulled “High” with a 50k
resistor.
SIGNAL NAME
PIN #TYPE
DESCRIPTION
0
1
0
1
0
100
110
75
120
Termination
TERSEL1
TERSEL0
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