參數(shù)資料
型號(hào)： XQ4005E
廠商： Xilinx, Inc.
英文描述： High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場(chǎng)可編程門(mén)陣列)
中文描述： 高可靠性的現(xiàn)場(chǎng)可編程門(mén)陣列（高可靠性現(xiàn)場(chǎng)可編程門(mén)陣列）
文件頁(yè)數(shù)： 6/34頁(yè)
文件大?。?/td> 529K
代理商： XQ4005E
QPRO
TM
XQ4000E/EX QML High-Reliability Field Programmable Gate Arrays
6
May 19, 1998 (Version 2.1)
XQ4000E CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer
(TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E/EX devices unless
otherwise noted.
Speed Grade
-3
-4
Units
Description
Symbol
Min
Max
Min
Max
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H to X/Y outputs
C inputs via H to X/Y outputs
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to COUT
CIN through function generators to X/Y outputs
CIN to COUT, bypass function generators
Sequential Delays
Clock K to outputs Q
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
T
ILO
T
IHO
T
HH1O
3.1
5.5
4.7
3.9
5.9
4.9
ns
ns
ns
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
2.6
4.4
1.7
4.4
0.7
4.4
6.8
2.9
5.0
1.0
ns
ns
ns
ns
ns
T
CKO
5.0
ns
T
ICK
T
IHCK
T
HH1CK
T
HH2CK
T
DICK
T
ECCK
T
RCK
3.0
4.6
4.1
3.8
2.4
3.0
4.0
4.0
6.1
5.0
4.8
3.0
4.0
4.2
ns
ns
ns
ns
ns
ns
ns
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