參數(shù)資料
型號(hào)： XQ4005E
廠商： Xilinx, Inc.
英文描述： High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場(chǎng)可編程門陣列)
中文描述： 高可靠性的現(xiàn)場(chǎng)可編程門陣列（高可靠性現(xiàn)場(chǎng)可編程門陣列）
文件頁(yè)數(shù)： 29/34頁(yè)
文件大?。?/td> 529K
代理商： XQ4005E
May 19, 1998 (Version 2.1)
29
XQ4028EX IOB Input Switching Characteristic Guidelines (Continued)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000EX devices unless
otherwise noted.
Note 1: For CMOS input levels, see the
“XQ4028EX Input Threshold Adjustments” on page 27
.
Note 2: For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Set-up and Hold
tables on
page 27
.
Speed Grade
Description
-4
Min
Units
Symbol
Setup Times
Pad to Clock (IK), no delay
Pad to Clock (IK), partial delay
Pad to Clock (IK), full delay
Pad to Clock (IK), via transparent Fast Capture Latch, no delay
Pad to Clock (IK), via transparent Fast Capture Latch, partial delay T
PICKFP
Pad to Fast Capture Latch Enable (OK), no delay
Pad to Fast Capture Latch Enable (OK), partial delay
Setup Times (TTL or CMOS Inputs)
Clock Enable (EC) to Clock (IK)
Hold Times
Pad to Clock (IK),
no delay
partial delay
full delay
Pad to Clock (IK) via transparent Fast
Capture Latch,
no delay
partial delay
full delay
Clock Enable (EC) to Clock (IK),
no delay
partial delay
full delay
Pad to Fast Capture Latch Enable (OK),
no delay
partial delay
T
PICK
T
PICKP
T
PICKD
T
PICKF
2.5
10.8
15.7
3.9
12.3
0.8
9.1
ns
ns
ns
ns
ns
ns
ns
T
POCK
T
POCKP
T
ECIK
0.3
ns
T
IKPI
T
IKPIP
T
IKPID
0
0
0
ns
ns
ns
T
IKFPI
T
IKFPIP
T
IKFPID
0
0
0
ns
ns
ns
T
IKEC
T
IKECP
T
IKECD
0
0
0
ns
ns
ns
T
OKPI
T
OKPIP
0
0
ns
ns
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