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參數(shù)資料
| 型號(hào)： | XQ4005E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場可編程門陣列) |
| 中文描述： | 高可靠性的現(xiàn)場可編程門陣列（高可靠性現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 20/34頁 |
| 文件大?。?/td> | 529K |
| 代理商： | XQ4005E |
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QPRO
TM
XQ4000E/EX QML High-Reliability Field Programmable Gate Arrays
20
May 19, 1998 (Version 2.1)
XQ4028EX CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XQ4000EX devices unless otherwise noted.
Speed Grade
-4
Units
Description
Symbol
Min
Max
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H’ to X/Y outputs
C inputs via H1 via H’ to X/Y outputs
C inputs via DIN/H2 via H’ to X/Y outputs
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to COUT
CIN through function generators to X/Y outputs
C
IN
to C
OUT
, bypass function generators
Carry Net Delay,
C
OUT
to
C
IN
Sequential Delays
Clock K to Flip-Flop outputs Q
Clock K to Latch outputs Q
Setup Time before Clock K
F/G inputs
F/G inputs via H’
C inputs via H0 through H’
C inputs via H1 through H’
C inputs via H2 through H’
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F’/G’
CIN input via F’/G’ and H’
Hold Time after Clock K
F/G inputs
F/G inputs via H’
C inputs via SR/H0 through H’
C inputs via H1 through H’
C inputs via DIN/H2 through H’
C inputs via DIN/H2
C inputs via EC
C inputs via SR, going Low (inactive)
Clock
Clock High time
Clock Low time
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
T
ILO
T
IHO
T
ITO
T
HH0O
T
HH1O
T
HH2O
T
CBYP
2.2
3.8
3.2
3.6
3.0
3.6
2.0
ns
ns
ns
ns
ns
ns
ns
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
T
NET
2.5
4.1
1.9
3.0
0.60
0.18
ns
ns
ns
ns
ns
ns
T
CKO
T
CKLO
2.2
2.2
ns
ns
T
ICK
T
IHCK
T
HH0CK
T
HH1CK
T
HH2CK
T
DICK
T
ECCK
T
RCK
T
CCK
T
CHCK
1.3
3.0
2.8
2.2
2.8
1.2
1.2
0.8
2.2
3.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
CKI
T
CKIH
T
CKHH0
T
CKHH1
T
CKHH2
T
CKDI
T
CKEC
T
CKR
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
T
CH
T
CL
3.5
3.5
ns
ns
T
RPW
T
RIO
3.5
4.5
ns
ns
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