- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375050 > XQ4005E (Xilinx, Inc.) High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場可編程門陣列) PDF資料下載
參數(shù)資料
| 型號： | XQ4005E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場可編程門陣列) |
| 中文描述： | 高可靠性的現(xiàn)場可編程門陣列（高可靠性現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 12/34頁 |
| 文件大?。?/td> | 529K |
| 代理商： | XQ4005E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
QPRO
TM
XQ4000E/EX QML High-Reliability Field Programmable Gate Arrays
12
May 19, 1998 (Version 2.1)
XQ4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XQ4000E/EX devices unless otherwise noted.
Speed Grade
Symbol
T
ICKOF
-3
-4
Units
Description
Device
XQ4005E
XQ4010E
XQ4013E
XQ4025E
Global Clock to Output
(fast) using OFF
(Max)
10.9
11.0
14.0
16.0
16.5
17.0
ns
ns
ns
ns
Global Clock to Output
(slew-limited) using OFF
T
ICKO
(Max)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
14.9
15.0
18.0
20.0
20.5
21.0
ns
ns
ns
ns
Input Setup Time, using IFF
(no delay)
T
PSUF
(Min)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
0.2
0
2.0
1.9
1.6
1.5
ns
ns
ns
ns
Input Hold Time, using IFF
(no delay)
T
PHF
(Min)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
5.5
6.5
4.6
6.0
7.0
8.0
ns
ns
ns
ns
Input Setup Time, using IFF
(with delay)
T
PSU
(Min)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
7.0
7.0
8.5
8.5
8.5
9.5
ns
ns
ns
ns
ns
ns
ns
ns
Input Hold Time, using IFF
(with delay)
T
PH
(Min)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
0
0
0
0
0
0
ns
ns
ns
ns
OFF = Output Flip-Flop IFF = Input Flip-Flop or Latch
OFF
Global Clock-to-Output Delay
.
X3202
T
PG
OFF
Global Clock-to-Output Delay
.
X3202
T
PG
IFF
D
X3201
SeInput
&
Hold
T
PG
IFF
D
X3201
SeInput
&
Hold
T
PG
IFF
D
X3201
SeInput
&
Hold
T
PG
IFF
D
X3201
SeInput
&
Hold
T
PG
相關PDF資料 |
PDF描述 |
|---|---|
| XQ4013XL-1CB240N | QML High-Reliability FPGAs |
| XQ4000XL | QML High-Reliability FPGAs |
| XQ4013XL-1BG228M | QML High-Reliability FPGAs |
| XQ4013XL-1BG228N | QML High-Reliability FPGAs |
| XQ4013XL-1BG240M | QML High-Reliability FPGAs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XQ4005E-3BG191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005E-3BG191N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005E-3BG196M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005E-3BG196N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005E-3CB191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
發(fā)布緊急采購，3分鐘左右您將得到回復。