參數(shù)資料
型號(hào)： XQ4005E
廠商： Xilinx, Inc.
英文描述： High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場(chǎng)可編程門陣列)
中文描述： 高可靠性的現(xiàn)場(chǎng)可編程門陣列（高可靠性現(xiàn)場(chǎng)可編程門陣列）
文件頁(yè)數(shù)： 10/34頁(yè)
文件大?。?/td> 529K
代理商： XQ4005E
QPRO
TM
XQ4000E/EX QML High-Reliability Field Programmable Gate Arrays
10
May 19, 1998 (Version 2.1)
XQ4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XQ4000E/EX devices unless otherwise noted.
Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
Speed Grade
-3
-4
Units
Description
Size
Symbol
Min
Max
Max
Write Operation
Address write cycle time
16x2
32x1
T
WC
T
WCT
8.0
8.0
8.0
8.0
ns
ns
Write Enable pulse width (High)
16x2
32x1
T
WP
T
WPT
4.0
4.0
4.0
4.0
ns
ns
Address setup time before WE
16x2
32x1
T
AS
T
AST
2.0
2.0
2.0
2.0
ns
ns
Address hold time after end of WE
16x2
32x1
T
AH
T
AHT
2.0
2.0
2.5
2.0
ns
ns
DIN setup time before end of WE
16x2
32x1
T
DS
T
DST
2.2
2.2
4.0
5.0
ns
ns
DIN hold time after end of WE
16x2
32x1
T
DH
T
DHT
2.0
2.0
2.0
2.0
ns
ns
Read Operation
Address read cycle time
16x2
32x1
T
RC
T
RCT
3.1
5.5
4.5
6.5
ns
ns
Data valid after address change
(no Write Enable)
16x2
32x1
T
ILO
T
IHO
3.1
5.5
3.9
5.9
ns
ns
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
16x2
32x1
T
ICK
T
IHCK
3.0
4.6
4.0
6.1
ns
ns
Read During Write
Data valid after WE goes active (DIN stable before
WE)
16x2
32x1
T
WO
T
WOT
6.0
7.3
10.0
12.0
ns
ns
Data valid after DIN
(DIN changes during WE)
16x2
32x1
T
DO
T
DOT
6.6
7.6
9.0
11.0
ns
ns
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
16x2
32x1
T
WCK
T
WCKT
6.0
6.8
8.0
9.6
ns
ns
Data setup time before clock K
16x2
32x1
T
DCK
T
DCKT
5.2
6.2
7.0
8.0
ns
ns
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