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參數(shù)資料
| 型號： | XQ4005E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場可編程門陣列) |
| 中文描述： | 高可靠性的現(xiàn)場可編程門陣列（高可靠性現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 28/34頁 |
| 文件大?。?/td> | 529K |
| 代理商： | XQ4005E |
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QPRO
TM
XQ4000E/EX QML High-Reliability Field Programmable Gate Arrays
28
May 19, 1998 (Version 2.1)
XQ4028EX IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000EX devices unless
otherwise noted.
Note 1: For CMOS input levels, see the
“XQ4028EX Input Threshold Adjustments” on page 27
.
Note 2: For set-up and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Set-up and Hold
tables on
page 27
.
.
Speed Grade
-4
Min
Units
Description
Clocks
Delay from FCL enable (OK) active edge to IFF clock (IK) active edge
Propagation Delays
Pad to I1, I2
Pad to I1, I2 via transparent input latch, no delay
Pad to I1, I2 via transparent input latch, partial delay
Pad to I1, I2 via transparent input latch, full delay
Pad to I1, I2 via transparent FCL and input latch, no delay
Pad to I1, I2 via transparent FCL and input latch, partial delay
Propagation Delays
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
FCL Enable (OK) active edge to I1, I2
(via transparent standard input latch)
Global Set/Reset
Minimum GSR Pulse Width
Delay from GSR input to any Q
FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch
Symbol
T
OKIK
3.2
Max
2.2
3.8
13.3
18.2
5.3
13.6
ns
T
PID
T
PLI
T
PPLI
T
PDLI
T
PFLI
T
PPFLI
ns
ns
ns
ns
ns
ns
T
IKRI
T
IKLI
T
OKLI
3.0
3.2
6.2
ns
ns
ns
T
MRW
T
RRI
13.0
22.8
ns
ns
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