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QPRO
TM
XQ4000E/EX QML High-Reliability Field Programmable Gate Arrays
30
May 19, 1998 (Version 2.1)
XQ4028EX IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values apply to all XQ4000EX devices unless otherwise noted.
Note 1: Output timing is measured at TTL threshold, with 35pF external capacitive loads.
Note 2: For CMOS output levels, see the
“XQ4028EX Output Level and Slew Rate Adjustments” on page 26
.
Speed Grade
-4
Units
Description
Symbol
Min
Max
Max
Propagation Delays
Clock (OK) to Pad
Output (O) to Pad
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid
Output MUX Select (OK) to Pad
Fast Path Output MUX Input (EC) to Pad
Slowest Path Output MUX Input (O) to Pad
T
OKPOF
T
OPF
T
TSHZ
T
TSONF
T
OKFPF
T
CEFPF
T
OFPF
7.4
6.2
4.9
6.2
6.7
6.2
7.3
6.0
5.0
4.1
5.0
5.4
5.0
5.9
ns
ns
ns
ns
ns
ns
ns
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup
Clock Enable (EC) to clock (OK) hold
T
OOK
T
OKO
T
ECOK
T
OKEC
0.6
0
0
0
ns
ns
ns
ns
Clock
Clock High
Clock Low
T
CH
T
CL
3.5
3.5
ns
ns
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Pad (XQ4028EX)
Delay from GSR input to any Pad (XQ4036EX)
T
MRW
T
RPO
T
RPO
13.0
30.2
31.4
ns
ns
ns