參數(shù)資料
型號： XC3S200A-4VQ100I
廠商： Xilinx Inc
文件頁數(shù)： 96/132頁
文件大小： 0K
描述： IC FPGA SPARTAN 3 100VQFP
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3A
LAB/CLB數(shù)： 448
邏輯元件/單元數(shù)： 4032
RAM 位總計： 294912
輸入/輸出數(shù)： 68
門數(shù)： 200000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
Pinout Descriptions
66
DS529-4 (v2.0) August 19, 2010
Package Pins by Type
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions vary by package, as shown in Table 58.
A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these I/O
depend on the device type and the package in which it is
available, as shown in Table 59. The table shows the
maximum number of single-ended I/O pins available,
assuming that all I/O-, INPUT-, DUAL-, VREF-, and
CLK-type pins are used as general-purpose I/O. AWAKE is
counted here as a dual-purpose I/O pin. Likewise, the table
shows the maximum number of differential pin-pairs
available on the package. Finally, the table shows how the
total maximum user-I/Os are distributed by pin type,
including the number of unconnected—N.C.—pins on the
device.
Not all I/O standards are supported on all I/O banks. The left
and right banks (I/O banks 1 and 3) support higher output
drive current than the top and bottom banks (I/O banks 0
and 2). Similarly, true differential output standards, such as
LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only
supported in the top or bottom banks (I/O banks 0 and 2).
Inputs are unrestricted. For more details, see the chapter
“Using I/O Resources” in UG331.
PWR
MGMT
Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated
pin and is powered by VCCAUX. AWAKE is a dual-purpose pin. Unless Suspend mode is
enabled in the application, AWAKE is available as a user-I/O pin.
SUSPEND, AWAKE
JTAG
Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has
four dedicated JTAG pins. These pins are powered by VCCAUX.
TDI, TMS, TCK, TDO
GND
Dedicated ground pin. The number of GND pins depends on the package used. All must
be connected.
GND
VCCAUX
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the
package used. All must be connected. VCCAUX can be either 2.5V or 3.3V. Set on board
and using CONFIG VCCAUX constraint.
VCCAUX
VCCINT
Dedicated internal core logic power supply pin. The number of VCCINT pins depends on
the package used. All must be connected to +1.2V.
VCCINT
VCCO
Along with all the other VCCO pins in the same bank, this pin supplies power to the output
buffers within the I/O bank and sets the input threshold voltage for some I/O standards. All
must be connected.
VCCO_#
N.C.
This package pin is not connected in this specific device/package combination but may be
connected in larger devices in the same package.
N.C.
Notes:
1.
# = I/O bank number, an integer between 0 and 3.
Table 57: Types of Pins on Spartan-3A FPGAs(Continued)
Type / Color
Code
Description
Pin Name(s) in Type
Table 58: Power and Ground Supply Pins by Package
Package
VCCINT
VCCAUX
VCCO
GND
VQ100
4
3
6
13
TQ144
4
8
13
FT256 (50A/200A/400A)
6
4
16
28
FT256 (700A/1400A)
15
10
13
50
FG320
6
8
16
32
FG400
9
8
22
43
FG484
15
10
24
53
FG676
23
14
36
77
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