參數(shù)資料
型號: XC3S200A-4VQ100I
廠商: Xilinx Inc
文件頁數(shù): 70/132頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3 100VQFP
標準包裝: 90
系列: Spartan®-3A
LAB/CLB數(shù): 448
邏輯元件/單元數(shù): 4032
RAM 位總計: 294912
輸入/輸出數(shù): 68
門數(shù): 200000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
DC and Switching Characteristics
42
DS529-3 (v2.0) August 19, 2010
Configurable Logic Block (CLB) Timing
Table 30: CLB (SLICEM) Timing
Symbol
Description
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Clock-to-Output Times
TCKO
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
–0.60
–0.68
ns
Setup Times
TAS
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
0.18
–0.36
–ns
TDICK
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
1.58
–1.88
–ns
Hold Times
TAH
Time from the active transition at the CLK input to the
point where data is last held at the F or G input
0
–0
–ns
TCKDI
Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input
0
–0
–ns
Clock Timing
TCH
The High pulse width of the CLB’s CLK signal
0.63
–0.75
–ns
TCL
The Low pulse width of the CLK signal
0.63
–0.75
–ns
FTOG
Toggle frequency (for export control)
0
770
0
667
MHz
Propagation Times
TILO
The time it takes for data to travel from the CLB’s F
(G) input to the X (Y) output
–0.62
–0.71
ns
Set/Reset Pulse Width
TRPW_CLB
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
1.33
–1.61
–ns
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
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