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參數(shù)資料
| 型號： | WED3DL3216V8BC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 16M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA119 |
| 封裝： | 17 X 23 MM, MO-163, BGA-119 |
| 文件頁數(shù)： | 21/27頁 |
| 文件大?。?/td> | 989K |
| 代理商： | WED3DL3216V8BC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WED3DL3216V
November, 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
Parameter
Symbol
Min
Max
Units
Power Supply Voltage
VCC/VCCQ
-1.0
+4.6
V
Input Voltage
VIN
-1.0
+4.6
V
Output Voltage
VOUT
-1.0
+4.6
V
Operating Temperature
TOPR
-0
+70
°C
Storage Temperature
TTSG
-55
+125
°C
Power Dissipation
PD
—
1.5
W
Short Circuit Output Current
IOS
—50mA
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
ABSOLUTE MAXIMUM RATINGS*
* Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions greater than those indicated in the operational sections of this specication is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Symbol
Type
Signal
Polarity
Function
CK
Input
Pulse
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock
CKE
Input
Level
Active High
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode
CE#
Input
Pulse
Active Low
CE# disable or enable device operation by masking or enabling all inputs except CK, CKE and
DQM.
RAS#, CAS#,
WE#
Input
Pulse
Active Low
When sampled at the positive rising edge of the clock, CAS#, RAS# and WE# dene the
operation to be executed by the SDRAM
BA0, BA1
Input
Level
Selects which SDRAM bank is to be active.
A0-12
Input
Level
During a Bank Activate command cycle, A0-12 denes the row address (RA0-12) when sampled
at the rising clock edge.
During a Read or Write command cycle, A0-8 denes the column address (CA0-8) when
sampled at the rising edge of the clock. In addition to the row address, A10/AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high,
autoprecharge is selected and BA0, BA1 denes the bank to be precharged. If A10/AP is low,
autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the
state of BA0, BA1. If A10/AP is low, than BA0, BA1 is used to dene which bank to precharge.
DQ
Input/Output
Level
Data Input/Output are multiplexed on the same pins
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED3DL3216V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16Mx32 SDRAM |
| WED3DL3216V-BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM MCP |
| WED3DL324V10BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SDRAM |
| WED3DL324V8BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SDRAM |
| WED3DL324V-BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM MCP |
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