參數(shù)資料
型號: WED3DL3216V8BC
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: DRAM
英文描述: 16M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA119
封裝: 17 X 23 MM, MO-163, BGA-119
文件頁數(shù): 16/27頁
文件大?。?/td> 989K
代理商: WED3DL3216V8BC
23
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WED3DL3216V
November, 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2
@ BURST LENGTH = FULL PAGE
NOTES:
1.
BRSW mode is enabled by setting As “High” at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is xed to “1” regardless of programmed burst length.
2.
When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the
case of BRSW write command, the next cycle starts the precharge.
CLOCK
CKE
CE#
RAS#
CAS#
ADDR
BA
A10/AP
CL = 2
WE#
DQM
01
2
3
4
56
78
9
10
11
12
13
14
15
16
17
18
19
DON’T CARE
DQ
CL = 3
Row Active
(A-Bank)
Precharge
(Both Banks)
Write
(A-Bank)
Read with
Auto Precharge
(A-Bank)
HIGH
Note 2
RAa
CAa
CBc
CAd
RAa
DAa0
QAb0
QAb1
DBc0
QAd1
QAd0
Write with
Auto Precharge
(A-Bank)
Read
(A-Bank)
CAb
Note 1
Note 3
Row Active
(B-Bank)
Row Active
(A-Bank)
Note 1
Note 3
RBb
RAc
RBb
RAc
DAa0
QAb0
QAb1
DBc0
QAd1
QAd0
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