參數(shù)資料
型號: W25Q80VZPIG
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 1M X 8 SPI BUS SERIAL EEPROM, DSO8
封裝: 6 X 5 MM, GREEN, WSON-8
文件頁數(shù): 31/61頁
文件大?。?/td> 1794K
代理商: W25Q80VZPIG
W25Q80, W25Q16, W25Q32
Publication Release Date: September 26, 2007
- 37 -
Preliminary - Revision B
10.2.19 Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure 19.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit.
The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any
page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory
Protection table).
Figure 19. Chip Erase Instruction Sequence Diagram
相關PDF資料
PDF描述
W25X16AVDAIZ 2M X 8 FLASH 2.7V PROM, PDIP8
W25X40AVSSIG 512K X 8 FLASH 2.7V PROM, PDSO8
W25X80AVDAIZ 1M X 8 FLASH 2.7V PROM, PDIP8
W25X80ALSSIG 1M X 8 FLASH 2.7V PROM, PDSO8
W25X40ALDAIZ 512K X 8 FLASH 2.7V PROM, PDIP8
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