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參數(shù)資料
| 型號： | W25Q80VZPIG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 1M X 8 SPI BUS SERIAL EEPROM, DSO8 |
| 封裝： | 6 X 5 MM, GREEN, WSON-8 |
| 文件頁數(shù)： | 26/61頁 |
| 文件大?。?/td> | 1794K |
| 代理商： | W25Q80VZPIG |
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W25Q80, W25Q16, W25Q32
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10.2.14 Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the
device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated
by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0)
and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the
instruction while data is being sent to the device. The Page Program instruction sequence is shown in
figure 14.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address
bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the
remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than
256 bytes (a partial page) can be programmed without having any effect on other bytes within the same
page. One condition to perform a partial page program is that the number of clocks can not exceed the
remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the
beginning of the page and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is
driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may
still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions
again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is
protected by the Block Protect (BP2, BP1, and BP0) bits.
Figure 14. Page Program Instruction Sequence Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W25X16AVDAIZ | 2M X 8 FLASH 2.7V PROM, PDIP8 |
| W25X40AVSSIG | 512K X 8 FLASH 2.7V PROM, PDSO8 |
| W25X80AVDAIZ | 1M X 8 FLASH 2.7V PROM, PDIP8 |
| W25X80ALSSIG | 1M X 8 FLASH 2.7V PROM, PDSO8 |
| W25X40ALDAIZ | 512K X 8 FLASH 2.7V PROM, PDIP8 |
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