參數(shù)資料
型號(hào)： V85C2256164SAS8
廠商： MOSEL-VITELIC
元件分類： DRAM
英文描述： 16M X 16 DDR DRAM, 0.8 ns, PBGA60
封裝： 0.80 X 1 MM PITCH, SOC, BGA-60
文件頁數(shù)： 59/61頁
文件大小： 814K
代理商： V85C2256164SAS8
7
MOSEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.4 October 2002
Signal Pin Description
Pin
Type
Signal
Polarity
Function
CK
Input
Pulse
Positive
Edge
The system clock input. All inputs except DQs and DMs are sampled on the rising edge
of CK.
CKE
Input
Level
Active High Activates the CK signal when high and deactivates the CK signal when low, thereby ini-
tiates either the Power Down mode, or the Self Refresh mode.
CS
Input
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS
WE
Input
Pulse
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
DQS
Input/
Output
Pulse
Active High Active on both edges for data input and output.
Center aligned to input data
Edge aligned to output data
A0 - A12
Input
Level
—
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends on the SDRAM organization:
64M x 4 DDR CAn = CA9, A11
32M x 8 DDR CAn = CA9
16M x 16 DDR CAn = CA8
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.
BA0,
BA1
Input
Level
—
Selects which bank is to be active.
DQx
Input/
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DM,
LDM,
UDM
Input
Pulse
Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if is high for x 16 LDM
corresponds to data on DQ0-DQ7, UDM corresponds to data on DQ8-DQ15.
QFC
Output
Level
Active Low FET Control: Output during every read and write access. Can be used to control isolation
switches on modules.
VDD, VSS
Supply
Power and ground for the input buffers and the core logic.
VDDQ
VSSQ
Supply
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
VREF
Input
Level
—
SSTL Reference Voltage for Inputs
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