參數(shù)資料
型號： V85C2256164SAS8
廠商： MOSEL-VITELIC
元件分類： DRAM
英文描述： 16M X 16 DDR DRAM, 0.8 ns, PBGA60
封裝： 0.80 X 1 MM PITCH, SOC, BGA-60
文件頁數(shù)： 29/61頁
文件大小： 814K
代理商： V85C2256164SAS8
35
MOSEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.4 October 2002
IDD Max Specifications and Conditions
(0°C < TA < 70°C, VDDQ=25V+ 0.2V, VDD=2.5 +0.2V)
Conditions
Version
Symbol
-6
-7
-7.5
-8
Unit
Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200,
133Mhz for DDR266A & DDR266B, 166Mhz for DDR333B; DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs changing once per clock cycle
IDD0
110
100
90
mA
Operating current - One bank operation; One bank open, BL=4
IDD1
140
120
100
mA
Percharge power-down standby current; All banks idle; power - down mode; CKE =
<VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for
DQ,DQS and DM
IDD2P
25
20
15
mA
Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min);
tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs
changing once per clock cycle; Vin = Vref for DQ,DQS and DM
IDD2F
45
38
35
mA
Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK =
100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable
with keeping >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM
IDD2Q
44
37
34
mA
Active power - down standby current; one bank active; power-down mode; CKE=< VIL (max);
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B, 166MHZ for DDR333B; Vin =
Vref for DQ,DQS and DM
IDD3P
25
20
15
mA
Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - pre-
charge; tRC=tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B, 166Mhz
for DDR333B; DQ, DQS and DM inputs changing twice per clock cycle; address and other control
inputs changing once per clock cycle
IDD3N
80
70
60
mA
Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active;
address and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200,
CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B, CL=2.5 at
tCK=166Mhz for DDR333B; 50% of data changing at every burst; lout = 0 m A
IDD4R
230
190
150
mA
Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active ad-
dress and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200,
CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS
inputs changing twice per clock cycle, 50% of input data changing at every burst
IDD4W
210
170
130
mA
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A
& DDR266B at 133Mhz, 12*tCK for DDR333B; distributed refresh
IDD5
200
190
180
mA
Self refresh current; CKE =< 0.2V; External clock should be on; tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B, 166Mhz for DDR333B.
Self refresh current; (Low Power)
IDD6
(normal)
33
3
mA
(L)
1.8
mA
Operating current - Four bank operation; Four bank interleaving with BL=4
IDD7
350
300
250
mA
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