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參數(shù)資料
| 型號： | V85C2256164SAS8 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 DDR DRAM, 0.8 ns, PBGA60 |
| 封裝： | 0.80 X 1 MM PITCH, SOC, BGA-60 |
| 文件頁數(shù)： | 16/61頁 |
| 文件大?。?/td> | 814K |
| 代理商： | V85C2256164SAS8 |
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23
MOSEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.4 October 2002
Read Interrupted by a Write
To interrupt a Burst Read with a Write command, a Burst Stop command must be asserted to stop the burst
read operation and 3-state the DQ bus. Additionally, control of the DQS bus must be turned around to allow
the memory controller to drive the data strobe signal (DQS) into the DDR SDRAM for the write cycles. Once
the Burst Stop command has been issued, a Write command can not be issued until a minimum delay or
latency (L
BST) has been satisfied. This latency is measured from the Burst Stop command and is equivalent
to the CAS latency programmed into the mode register. In instances where CAS latency is measured in half
clock cycles, the minimum delay (L
BST) is rounded up to the next full clock cycle (i.e., if CL=2 then LBST=2, if
CL=2.5 then L
BST=3). It is illegal to interrupt a Read with autoprecharge command with a Write command.
Read Interrupted by Burst Stop Command Followed by a Write Command Timing
Write Interrupted by a Write
A Burst Write can be interrupted before completion by a new Write command to any bank. When the pre-
vious burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new
address. The data from the first Write command continues to be input into the device until the Write Latency
of the interrupting Write command is satisfied (WL=1) At this point, the data from the interrupting Write com-
mand is input into the device. Write commands can be issued on each rising edge of the system clock. It is
illegal to interrupt a Write with autoprecharge command with a Write command.
Write Interrupted by a Write Command Timing
(CAS Latency = 2; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
BST
NOP
Write
NOP
D0
D1
Read
D0
D1
D2
D3
CK, CK
Command
DQS
DQ
T9
LBST
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
WriteA
NOP
WriteB
NOP
DA0 DA1 DB0 DB1 DB2 DB3
CK, CK
Command
DQS
DQ
DM
T9
Write Latency
DM0 DM1 DM0 DM1 DM2 DM3
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