參數(shù)資料
型號： V85C2256164SAS8
廠商： MOSEL-VITELIC
元件分類： DRAM
英文描述： 16M X 16 DDR DRAM, 0.8 ns, PBGA60
封裝： 0.80 X 1 MM PITCH, SOC, BGA-60
文件頁數(shù)： 30/61頁
文件大?。?/td> 814K
代理商： V85C2256164SAS8
36
V58C2256(804/404/164)S Rev. 1.4 October 2002
MOSEL VITELIC
V58C2256(804/404/164)S
AC Operating Conditions & Timming Specification
AC Operating Conditions
Note:
1.Vih(max) = 4.2V. The overshoot voltage duration is < 3ns at VDD.
2. Vil(min) = -1.5V. The undershoot voltage duration is < 3ns at VSS.
3. VID is the magnitude of the difference between the input level on CK and the input on CK.
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
ELECTRICAL CHARACTERISTICS AND AC TIMING for PC333/PC266/PC200 -Absolute
Specifications
(Notes: 1-5, 14-17) (0°C < T A < 70°C; VDDQ = +2.5V ±0.2V, +2.5V ±0.2V)
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
V
1
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
VREF - 0.31
V
2
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
VDDQ+0.6
V
3
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
4
AC CHARACTERISTICS
-6
-7
-75
-8
PARAMETER
SYM-
BOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN MAX
UNIT
SNOTES
Access window of DQs from CK/CK
tAC
-0.7
0.7
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
30
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
30
Clock cycle time
CL = 2.5
tCK (2.5)
6
12
7
12
7.5
12
8
12
ns
52
CL = 2
tCK (2)
7.5
12
7.5
12
10
12
10
12
ns
52
DQ and DM input hold time relative to
DQS
tDH
0.45
0.5
0.6
ns
26,31
DQ and DM input setup time relative to
DQS
tDS
0.45
0.5
0.6
ns
26,31
DQ and DM input pulse width (for each in-
put)
tDIPW
1.5
1.75
2
ns
31
Access window of DQS from CK/CK
tDQSCK
-0.6
0.6
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid,
per group, per access
tDQSQ
0.45
0.5
0.6
ns
25,26
Write command to first DQS latching tran-
sition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising - setup time
tDSS
0.2
tCK
DQS falling edge from CK rising - hold
time
tDSH
0.2
tCK
Half clock period
tHP
tCH,
tCL
tCH,
tCL
tCH,
tCL
tCH,
tCL
ns
34
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