參數(shù)資料
型號(hào)： V85C2256164SAS8
廠商： MOSEL-VITELIC
元件分類： DRAM
英文描述： 16M X 16 DDR DRAM, 0.8 ns, PBGA60
封裝： 0.80 X 1 MM PITCH, SOC, BGA-60
文件頁(yè)數(shù)： 38/61頁(yè)
文件大?。?/td> 814K
代理商： V85C2256164SAS8
43
MOSEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.4 October 2002
43. Note 43 is not used.
44. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may
be 1.35V maximum during power up, even if VDD /VDDQ are 0 volts, provided a minimum of 42 ohms of series re-
sistance is used between the VTT supply and the input pin.
45. Note 45 is not used.
46. tRAP t RCD.
47. Note 47 is not used.
48. Random addressing changing 50% of data changing at every transfer.
49. Random addressing changing 100% of data changing at every transfer.
50. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO
REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later.
51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F
except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are
similar, IDD2F is “worst case.”
52. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed
by 200 clock cycles.
Max
imum
Nominal
high
Nominal low
Nominal
high
Minimum
Maxim
um
80
70
60
50
40
30
20
10
0.0
0.5
1.0
1.5
2.0
2.5
0.0
-120
-100
-80
-60
-40
-20
0
0.5
1.0
1.5
2.0
2.5
0
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