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參數(shù)資料
| 型號： | V85C2256164SAS8 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 DDR DRAM, 0.8 ns, PBGA60 |
| 封裝： | 0.80 X 1 MM PITCH, SOC, BGA-60 |
| 文件頁數(shù)： | 15/61頁 |
| 文件大?。?/td> | 814K |
| 代理商： | V85C2256164SAS8 |
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22
V58C2256(804/404/164)S Rev. 1.4 October 2002
MOSEL VITELIC
V58C2256(804/404/164)S
Data Mask Function
The DDR SDRAM has a Data Mask function that is used in conjunction with the Write cycle, but not the
Read cycle. When the Data Mask is activated (DM high) during a Write operation, the Write is blocked (Mask
to Data Latency = 0).
When issued, the Data Mask must be referenced to both the rising and falling edges of Data Strobe.
Data Mask Timing
Burst Interruption
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by issuing a new Read command to any
bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length
starting with the new address. The data from the first Read command continues to appear on the outputs until
the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting
Read command appears on the bus. Read commands can be issued on each rising edge of the system clock.
It is illegal to interrupt a Read with autoprecharge command with a Read command.
Read Interrupted by a Read Command Timing
(CAS Latency = Any; Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
D0
D1
D2
D3
D4
D5
D6
D7
NOP
Write
CK, CK
Command
DQS
DQ
DM
T9
tDMDQSS
tDMDQSH
(CAS Latency = 2; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
ReadB
NOP
DA0 DA1 DB0 DB1
ReadA
DB2 DB3
CK, CK
Command
DQS
DQ
T9
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