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參數(shù)資料
| 型號： | V85C2256164SAS8 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 DDR DRAM, 0.8 ns, PBGA60 |
| 封裝： | 0.80 X 1 MM PITCH, SOC, BGA-60 |
| 文件頁數(shù)： | 24/61頁 |
| 文件大小： | 814K |
| 代理商： | V85C2256164SAS8 |
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30
V58C2256(804/404/164)S Rev. 1.4 October 2002
MOSEL VITELIC
V58C2256(804/404/164)S
NOTE: (continued)
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. Once tRCD is met, the bank will be in the “row active” state.
Read w/Auto-Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE
enabled and ends when tRP has been met. Once tRP is met, the bank will
be in the idle state.
Write w/Auto-Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE
enabled and ends when tRP has been met. Once tRP is met, the bank will
be in the idle state.
5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be
applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
tRC is met. Once tRFC is met, the DDR SDRAM will be in the “all banks
idle” state.
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends
when tMRD has been met. Once tMTC is met, the DDR SDRAM will be in
the “all banks idle” state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. Once tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle and no bursts are in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO PRECHARGE
enabled and READs or WRITEs with AUTO PRECHARGE disabled.
11. Requires appropriate DM masking.
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