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參數資料
| 型號： | V85C2256164SAS8 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 DDR DRAM, 0.8 ns, PBGA60 |
| 封裝： | 0.80 X 1 MM PITCH, SOC, BGA-60 |
| 文件頁數： | 26/61頁 |
| 文件大?。?/td> | 814K |
| 代理商： | V85C2256164SAS8 |
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32
V58C2256(804/404/164)S Rev. 1.4 October 2002
MOSEL VITELIC
V58C2256(804/404/164)S
NOTE: (continued)
Read with Auto Precharge Enabled: See following text
Write with Auto Precharge Enabled: See following text
3a. The Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states can each be broken
into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge
period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the
earliest possible PRECHARGE command that still accesses all of the data in the burst. For Write with Auto
Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was
disabled. The access period starts with registration of the command and ends where the precharge period
(or tRP) begins.
During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled
states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied; during the
access period, only ACTIVE and PRECHARGE commands to the other bank may be applied. In either case, all
other related limitations apply (e.g. contention between READ data and WRITE data must be avoided).
4. AUTO REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the
current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO PRECHARGE
enabled and READs or WRITEs with AUTO PRECHARGE disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of data output.
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