參數(shù)資料
型號(hào)： V85C2256164SAS8
廠商： MOSEL-VITELIC
元件分類(lèi)： DRAM
英文描述： 16M X 16 DDR DRAM, 0.8 ns, PBGA60
封裝： 0.80 X 1 MM PITCH, SOC, BGA-60
文件頁(yè)數(shù)： 2/61頁(yè)
文件大小： 814K
代理商： V85C2256164SAS8
10
V58C2256(804/404/164)S Rev. 1.4 October 2002
MOSEL VITELIC
V58C2256(804/404/164)S
Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising
edge of the clock. The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0 and
BA1) are supported. The Bank Activate command must be applied before any Read or Write operation can
be executed. The delay from the Bank Activate command to the first Read or Write command must meet or
exceed the minimum RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be pre-
charged before another Bank Activate command can be applied to the same bank. The minimum time interval
between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay
time (tRRD min).
Bank Activation Timing
Read Operation
With the DLL enabled, all devices operating at the same frequency within a system are ensured to have
the same timing relationship between DQ and DQS relative to the CK input regardless of device density, pro-
cess variation, or technology generation.
The data strobe signal (DQS) is driven off chip simultaneously with the output data (DQ) during each read
cycle. The same internal clock phase is used to drive both the output data and data strobe signal off chip to
minimize skew between data strobe and output data. This internal clock phase is nominally aligned to the
input differential clock (CK, CK) by the on-chip DLL. Therefore, when the DLL is enabled and the clock fre-
quency is within the specified range for proper DLL operation, the data strobe (DQS), output data (DQ), and
the system clock (CK) are all nominally aligned.
Since the data strobe and output data are tightly coupled in the system, the data strobe signal may be de-
layed and used to latch the output data into the receiving device. The tolerance for skew between DQS and
DQ (tDQSQ) is tighter than that possible for CK to DQ (tAC) or DQS to CK (tDQSCK).
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
(CAS Latency = 2; Burst Length = Any)
tRRD(min)
tRP(min)
tRC
tRCD(min)
Begin Precharge Bank A
CK, CK
BA/Address
Command
Bank/Col
Read/A
Bank/Row
Activate/A
Activate/B
Pre/A
Bank/Row
Activate/A
Bank
Bank/Row
tRAS(min)
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