
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT)
User’s Manual U14579EJ2V0UM
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Bit
Name
Function
5
REQ_Enable
Controls REQ# signal output timing.
1: PCICLK (internal clock) asynchronous output
0: PCICLK synchronous output
4:3
RFU
Reserved. Write 0 to these bits. 0 is returned after a read.
2
Status Change Standby
Device status relative to power status transition control.
1: Can correspond
0: Cannot correspond
1:0
Power Status
Power status control
11: D3 (PCICLK stopped, device power off)
10: D2 (PCICLK stopped, device power on)
01: Reserved
00: D0 (PCICLK full mode)
Remarks 1. Always use the default setting (synchronous) for the REQ_Enable bit. If the asynchronous setting is
used, the PCI specifications will be violated.
2. When the PC_mode bit = 0, the Power Status area is disabled. The Power Status area can be read
or written from the system, but can only be read from the USB host controller (HC).
3. When the PC_mode bit = 0, the Wakeup_Status bit is disabled. When the PC_mode bit = 1 and the
Power Status area = 10, the Wakeup_Status bit is set to 1 when a resume from the USB is detected.
At this time, if the Wakeup_Enable bit is 1, set the WAKE signal (internal signal) to active. This bit is
cleared when 1 is written to it and the WAKE signal is set to inactive at the same time. The above
operations occur only when the RHSC bit of the HcInterruptEnable register is set.
4. When the PC_mode bit = 0, the Wakeup_Enable bit is disabled.
5. After 10 or 11 is set in the Power Status area, 0 is displayed in the Status Change Standby bit until
the status change can actually occur, and 1 is displayed when the change can occur. Once the
Status Change Standby bit becomes 1 after 10 or 11 is set in the Power Status area, it cannot return
to 0.