
User’s Manual U14579EJ2V0UM
10
CONTENTS
CHAPTER 1 OVERVIEW ..........................................................................................................................25
1.1
Features .....................................................................................................................................25
1.2
Ordering Information................................................................................................................26
1.3
Internal Block Configuration ...................................................................................................26
1.4
PCI Device Configuration.........................................................................................................28
1.5
Lists of Registers......................................................................................................................29
CHAPTER 2 PIN FUNCTIONS ................................................................................................................44
2.1
Pin Configuration......................................................................................................................44
2.2
Pin Function Lists.....................................................................................................................50
2.2.1
PCI bus interface signals..........................................................................................................50
2.2.2
USB interface signals ...............................................................................................................50
2.2.3
AC-Link interface signals..........................................................................................................50
2.2.4
PC card interface signals .........................................................................................................51
2.2.5
Keyboard interface signals .......................................................................................................54
2.2.6
PS/2 interface signals...............................................................................................................54
2.2.7
Touch panel interface signals...................................................................................................55
2.2.8
Audio interface signal ...............................................................................................................55
2.2.9
General-purpose I/O signals ....................................................................................................55
2.2.10
Interrupt interface signal...........................................................................................................56
2.2.11
Clock interface signals .............................................................................................................56
2.2.12
Test interface signals ...............................................................................................................56
2.2.13
Power supplies and grounds ....................................................................................................57
2.3
Pin Status and Recommended Connection Examples .........................................................58
2.4
Clock Oscillator Connection....................................................................................................62
CHAPTER 3 BCU (BUS CONTROL UNIT) ...........................................................................................64
3.1
General.......................................................................................................................................64
3.2
Register Set ...............................................................................................................................64
3.2.1
VID (offset address: 0x00 to 0x01) ...........................................................................................65
3.2.2
DID (offset address: 0x02 to 0x03)...........................................................................................65
3.2.3
PCICMD (offset address: 0x04 to 0x05)...................................................................................66
3.2.4
PCISTS (offset address: 0x06 to 0x07) ....................................................................................67
3.2.5
RID (offset address: 0x08) .......................................................................................................68
3.2.6
CLASSC (offset address: 0x09 to 0x0B) ..................................................................................68
3.2.7
CACHELS (offset address: 0x0C) ............................................................................................68
3.2.8
MLT (offset address: 0x0D) ......................................................................................................69
3.2.9
HEDT (offset address: 0x0E)....................................................................................................69
3.2.10
BIST (offset address: 0x0F) .....................................................................................................69
3.2.11
BADR (offset address: 0x10 to 0x13) .......................................................................................70