
User’s Manual U14579EJ2V0UM
23
LIST OF TABLES (2/3)
Table No.
Title
Page
3-1
BCU Configuration Registers ......................................................................................................................... 64
4-1
DMAAU Registers .......................................................................................................................................... 76
5-1
DMA Priority Levels........................................................................................................................................ 81
5-2
DCU Registers ............................................................................................................................................... 81
6-1
CMU Registers ............................................................................................................................................... 87
7-1
Assignment of Sampling Clocks and Interrupt Sources ................................................................................. 92
7-2
ICU Registers ................................................................................................................................................. 93
8-1
GPIO Pin Outline.......................................................................................................................................... 107
8-2
GIU Registers............................................................................................................................................... 108
8-3
Correspondences Between Interrupt Mask and Interrupt Hold .................................................................... 122
8-4
Alternate Function Correspondence Table of VRC4173................................................................................ 124
9-1
PIU Registers ............................................................................................................................................... 131
9-2
PIUCNTREG Register Bit Manipulation and States ..................................................................................... 134
9-3
PIUASCNREG Register Bit Manipulation and States................................................................................... 140
9-4
Detected Data and Page Buffers.................................................................................................................. 143
9-5
A/D Ports and Data Buffers .......................................................................................................................... 144
9-6
Mask Clear During Scan Sequencer Operation ........................................................................................... 145
9-7
Relationships Among TPX, TPY, ADX, ADY, TPEN, ADIN, and AUDIOIN Pins and States........................ 148
10-1
AIU Registers ............................................................................................................................................... 152
11-1
KIU Registers ............................................................................................................................................... 166
12-1
PS2CH1 Registers ....................................................................................................................................... 182
12-2
PS2CH2 Registers ....................................................................................................................................... 182
13-1
CARDU Configuration Registers .................................................................................................................. 188
13-2
ExCA Registers ............................................................................................................................................ 223
13-3
ExCA Extended Registers............................................................................................................................ 225
13-4
CardBus Socket Registers ........................................................................................................................... 258
13-5
Registers Related to Memory Windows ....................................................................................................... 268
13-6
Registers Related to I/O Windows ............................................................................................................... 269
13-7
Interrupt Sources and Corresponding Masks............................................................................................... 270