參數(shù)資料
型號(hào)： TP3410J
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字傳輸電路
英文描述： TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver
中文描述： DATACOM, DIGITAL SLIC, CDIP28
封裝： CERAMIC, DIP-28
文件頁(yè)數(shù)： 8/32頁(yè)
文件大?。?/td> 436K
代理商： TP3410J
Functional Description
(Continued)
4.2 Embedded Operations Channel
The EOC channel consists of 2 complete 12-bit messages
per superframe, distributed through the M1, M2 and M3 bits
of each half-superframe as shown in Table I. Each message
is composed of 3 fields; a 3-bit address identifying the mes-
sage destination, a 1-bit indicator for the data mode, i.e.,
encoded message or raw data, and an 8-bit information
byte. The Microwire port or GCI Monitor Channel provides
access to the complete 12 bits of every message in the TX
EOC and the RXEOC Registers. If one of the defined en-
coded messages is received, e.g., Send Corrupted CRC,
then the appropriate Command Register instruction must be
written to the device to invoke the function.
4.3 M4 Bits
The M4 bit position of every frame is a transparent channel
in which are transmitted data bits loaded from the M4 Trans-
mit Register TXM4, one byte per superframe. On the re-
ceive side the M4 bits from one complete superframe are
sent to a checking circuit which holds each new M4 byte
and compares it against the previous M4 byte(s) for valida-
tion prior to sending it to the RXM4 Receive Register; Regis-
ter OPR provides several options for control of this valida-
tion.
4.4 Spare M5 And M6 Bits
Overhead bits M5 and M6 in frame 1 (M51 and M61) and
M5 in frame 2 (M52) are transparently transmitted from the
Transmit M56 Spare Bit Register to the line. In the receive
direction, data from these bit positions is sent to a checking
circuit which holds the new M5/M6 spare bits and com-
pares them against the previous M5/M6 bits for validation
prior to sending them to the Receive M56 Spare Bit Regis-
ter; the OPR Register provides several options for control of
this validation.
4.5 CRC Circuit
In the transmit direction an on-chip crc calculation circuit
automatically generates a checksum of the 2B
a
D
a
M4 bits
using the polynomial x12
a
x11
a
x3
a
x2
a
x
a
1. Once per
superframe the crc is transmitted in the specified M5 and
M6 bit positions (see Table I). In the receive direction a
checksum is again calculated on the same bits as they are
received and, at the end of the superframe, compared
against the crc transmitted with the data. The result of this
comparison generates a ‘‘Far End Block Error’’ bit (the febe
bit), which is transmitted back towards the other end of the
DSL in the next superframe. If there are no errors in a super-
frame, febe is set
e
1, and if there is one or more errors
febe is set
e
0.
The TP3410 also includes a readable 8-bit Block Error
Counter BEC1, which is decremented by 1 each superframe
in which febe
e
0 or nebe
e
0 is received. Section 10.5
describes the operation of this counter.
On first application of power, and after the software reset
(X’1880, X’1800), both the ECT1 as well as BEC1 are initial-
ized to X’FF. See the Block Error Counter section for more
details.
5.0 DIGITAL INTERFACE: ALL FORMATS
5.1 Clocking
In LT applications (network end of the Loop), the Digital
System Interface (DSI) normally accepts BCLK and FS sig-
nals from the network, requiring the selection of DSI or GCI
Slave mode in Register CR1. A Digital Phase-Locked Loop
(DPLL
Y
2) on the TP3410 allows the MCLK frequency to be
plesiochronous (i.e. free-running) with respect to the net-
work clocks, (BCLK and the 8 kHz FSa input). With a toler-
ance on the MCLK oscillator of 15.36 MHz
g
100 ppm, the
lock-in range of DPLL2 allows the network clock frequency
to deviate up to
g
50 ppm from nominal.
In NT applications, when the device is in NT mode and is
slaved to loop timing recovered from the received line sig-
nal, DSI or GCI Master mode should normally be selected.
In this case BCLK, FS and SCLK (15.36 MHz) signals are
outputs which are phase-locked to the recovered clock. A
slave-slave mode is also provided, however, in which the
Digital Interface data buffers on the TP3410 allow BCLK
and FSa/b to be input from an external source, which must
be frequency-locked (but may take an arbitrary phase) to
the received line signal; in this case DSI or GCI Slave mode
should be selected.
5.2 Data Buffers
The TP3410 buffers the 2B
a
D data at the Digital Interface
in elastic FIFOs, which are 3 frames deep in each direction.
When the Digital Interface is a timing slave these FIFOs
compensate for relative jitter and wander between the Digi-
tal Interface clocks (BCLK and FSa/b) and bit and frame
timing at the Line Interface. Each buffer can absorb wander
up to 18
m
s in
t
10 secs without ‘‘slip’’, exceeding CCITT
recommendation Q.502. Excessive wander causes a con-
trolled slip of one complete frame.
6.0 DIGITAL INTERFACE DATA FORMATS IN
MICROWIRE MODE (MW
e
1)
When the MW pin is tied high to enable the Microwire Port
for control and status, the Digital System Interface on the
TP3410 provides a choice of four multiplexed formats for
the B and D channel data, as shown in Figure 3. These
apply in both LT and NT modes of the device, and selection
is made via Register CR1. Selection of DSI Master or Slave
mode must also be made in CR1. Within each format there
is also an independent selection available to either multiplex
the D channel (Tx and Rx) data on the same pins as the B
channels, or via the separate D-channel access pins, DCLK,
Dx and Dr, see Section 6.3.
Format 1: In Format 1, the 2B
a
D data transfer is assigned
to the first 18 bits of the frame on the Bx and Br
pins. Channels are assigned as follows: B1 (8
bits), B2 (8 bits), D (2 bits), with the remaining
bits ignored until the next frame sync pulse.
When the D channel port is enabled (see CR2),
only the 2 B channels use the Bx and Br pins; the
D bits are assigned to the 17th and 18th bits of
the frame on the Dx and Dr pins. Figure 3-1
shows this format in DSI Slave Mode, andFigure
3-4 shows DSI Master Mode.
8
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