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參數(shù)資料
| 型號： | TP3410J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
| 中文描述： | DATACOM, DIGITAL SLIC, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 436K |
| 代理商： | TP3410J |
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Functional Description
(Continued)
8.2 GCI Frame Structure
Figure 7 shows the frame structure at the GCI interface.
One GCI channel supports one TP3410 using a bandwidth
of 256 kbit/s, consisting of the following channels multi-
plexed together in an 8 kHz frame:
D B1 channel at 8 bits per frame;
D B2 channel at 8 bits per frame;
D Monitor (M) channel at 8 bits per frame;
D Signalling and Control (SC) channel, which is structured
as follows:
D Channel at 2 bits per frame;
C/I channel at 4 bits per frame;
A bit, for acknowledgement of M channel bytes;
E bit, which indicates byte boundaries when multiple-
byte messages are transferred via the M channel.
8.3 Monitor Channel
The GCI Monitor channel (byte 3) is used to access all the
Command Registers shown in Table II, with the exception of
the Activation Control Register, and all the Status Registers
shown in Table III with the exception of the Activation Indi-
cation Register. Each access to or from one of the listed
registers requires a 2-byte message transfer. As shown in
Tables II and III, the first byte from the originating device
contains the register address, and the second byte is the
data byte. Status Registers originate messages in the Moni-
tor channel under control of the Interrupt Stack (in the same
manner as when the TP3410 is used in Microwire Mode). In
addition a protocol is used, based on the E and A bits in
byte 4, to provide an acknowledgement of each Monitor
channel byte in either direction, see Figure 8.
When no Monitor Channel message is being transferred,
the E bit, and the A bit in the reverse direction, are high-im-
pedance (and pulled high by the external resistor if no other
device is active in that channel). To initiate a transfer, a
device must first verify that it has received the A bit
e
1 for at
least 2 consecutive GCI frames from the other device be-
fore starting the transfer. It then sends the first byte in the
Monitor channel, with the associated E bit
e
0, and repeats
the byte in the next GCI frame. Normally, the receiving de-
vice will verify receiving the same byte in 2 consecutive
frames and acknowledge this by setting A
e
0 for at least 2
frames. If not, the message is aborted by sending A
e
0 for
only 1 frame.
On detecting the acknowledgement, the sending device
then sends the 2nd of the 2 bytes in 2 consecutive GCI
frames (or until it is acknowledged), with E
e
1 to indicate
this is the last byte of the transfer. The receiver verifies this
byte is the same for 2 frames and sends an acknowledge-
ment by sending A
e
1 in the next frame. If an abort is re-
quired, the receiver will maintain A
e
1 for another frame. If a
Monitor channel message originated by the TP3410 is
aborted, it will repeat the complete message until it is suc-
cessfully acknowledged.
8.4 C/I Channel
The C/I (Command/Indicate) channel in GCI byte 4 is used
solely to access the Activation Control Register and the Ac-
tivation Indication Register in the TP3410. A complete de-
scription of these registers is found in Section 11, including
the coding of the 4-bit messages. Unlike the Microwire
Mode of the device, however, the contents of these 2 regis-
ters are transferred repeatedly in the C/I channel, once per
GCI frame. A change in transmit message is originated by a
change in the Activation Indication Register, while a change
in received message is verified in 2 consecutive GCI frames
before updating the Activation Control Register and taking
the appropriate action.
TL/H/9151–16
Note 1:
As an output (GCI Master) FS
a
is high for 8-bit intervals (16 BCLK cycles). As an input (GCI Slave) FS
a
must be high for
t
1 BCLK cycle.
Note 2:
The FSb output is provided only in GCI Master Mode.
FIGURE 7. GCI Frame Structure is an Example of Multiplex Mode with BCLK
e
4.096 MHz
TL/H/9151–27
FIGURE 8. GCI Monitor Channel and E and A Bit Protocol
14
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